AD5545/AD5555

Data Sheet

Rev. G | Page 6 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5545/

AD5555

TOP VIEW

(Not to Scale)

8

7

6

5

1

4

3

2

9

10

11

12

16

13

14

15

CS

DGND

CLK

MSB

LDAC

RS

SDI

02918- 0- 002

Figure 4. 16-Lead TSSOP

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Establish voltage output for DAC A by connecting this pin to an external amplifier output.

2

DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can

3

DAC A Current Output.

4

DAC A Analog Ground.

5

DAC B Analog Ground.

6

DAC B Current Output.

7

DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage.

8

9

SDI

Serial Data Input. Input data loads directly into the shift register.

10

RS

Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or midscale. Register

Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and 0x2000 for AD5555 when

MSB = 1.

11

CS

Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register

data to the input register when CS/LDAC returns high. This does not affect LDAC operation.

12

DGND

Digital Ground Pin.

13

Positive Power Supply Input. Specified range of operation 5 V ± 10%.

14

MSB

MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on.

Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can also be tied

15

LDAC

Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC

registers. Asynchronous active low input. See Table 7 and Table 8 for operation.

16

CLK

Clock Input. Positive edge clocks data into shift register.