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AD9852/PCB Datasheet(PDF) 33 Page - Analog Devices

Part # AD9852/PCB
Description  CMOS 300 MSPS Complete DDS
PDF  52 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9852/PCB Datasheet(HTML) 33 Page - Analog Devices

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AD9852
Rev. E | Page 33 of 52
A<5:0>
D<7:0>
RD
A1
D1
A2
D2
A3
D3
tRDHOZ
tRDLOV
tAHD
tADV
SPECIFICATION
tADV
tAHD
tRDLOV
tRDHOZ
VALUE
15ns
5ns
15ns
10ns
DESCRIPTION
ADDRESS TO DATA VALID TIME (MAXIMUM)
ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)
RD LOW TO OUTPUT VALID (MAXIMUM)
RD HIGH TO DATA THREE-STATE (MAXIMUM)
Figure 49. Parallel Port Read Timing Diagram
D<7:0>
D1
D2
D3
SPECIFICATION
tASU
tDSU
tADH
tDHD
tWRLOW
tWRHIGH
tWR
VALUE
8.0ns
3.0ns
0ns
0ns
2.5ns
7ns
10.5ns
DESCRIPTION
ADDRESS SETUP TIME TO WR SIGNAL ACTIVE
DATA SETUP TIME TO WR SIGNAL ACTIVE
ADDRESS HOLD TIME TO WR SIGNAL INACTIVE
DATA HOLD TIME TO WR SIGNAL INACTIVE
WR SIGNAL MINIMUM LOW TIME
WR SIGNAL MINIMUM HIGH TIME
MINIMUM WRITE TIME
tWR
A<5:0>
A1
A2
A3
tASU
tAHD
tWRHIGH
tWRLOW
tDHD
tDSU
WR
Figure 50. Parallel Port Write Timing Diagram
Table 10. Serial I/O Pin Requirements
Pin Number
Mnemonic
Serial I/O Description
1 to 8
D [7:0]
The parallel data pins are not active; tie these pins to VDD or GND.
14 to 16
A [5:3]
The A5, A4, and A3 parallel address pins are not active; tie these pins to VDD or GND.
17
A2/IO RESET
IO RESET.
18
A1/SDO
SDO.
19
A0/SDIO
SDIO.
20
I/O UD CLK
Update Clock. Same functionality for serial mode as parallel mode.
21
WR/SCLK
SCLK.
22
RD/CS
CS—Chip Select.



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