AD9852SLASHPCB datasheet(14/52 Pages) AD

14 / 52 page

AD9852

Rev. E | Page 14 of 52

Figure 18 and Figure 19 show the residual phase noise performance of the AD9852 when operating with a 300 MHz reference clock with

the REFCLK multiplier bypassed vs. a 30 MHz reference clock with the REFCLK multiplier enabled at 10×.

CENTER 112.469MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

50kHz/

SPAN 500kHz

Figure 16. A Slight Change in Tuning Word Yields Dramatically Better Results;

112.469 MHz with All Spurs Shifted Out-of-Band, 300 MHz REFCLK

CENTER 39.1MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

5kHz/

SPAN 50kHz

Figure 17. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,

200 MHz REFCLK with REFCLK Multiplier Bypassed

FREQUENCY (Hz)

–100

–110

–150

–120

–130

–140

–160

–170

100

100k

10k

AOUT = 80MHz

AOUT = 5MHz

Figure 18. Residual Phase Noise,

300 MHz REFCLK with REFCLK Multiplier Bypassed

FREQUENCY (Hz)

–90

–100

–140

–110

–120

–130

–150

–160

100

100k

10k

AOUT = 80MHz

AOUT = 5MHz

Figure 19. Residual Phase Noise,

30 MHz REFCLK with REFCLK Multiplier = 10×

DAC CURRENT (mA)

1015

2025

Figure 20. SFDR vs. DAC Current, 59.1 AOUT,

300 MHz REFCLK with REFCLK Multiplier Bypassed

FREQUENCY (MHz)

620

615

610

605

600

595

590

100

120

140

Figure 21. Supply Current vs. Output Frequency (Variation Is Minimal,

Expressed as a Percentage, and Heavily Dependent on Tuning Word)

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