HN58C256AI Series

R10DS0218EJ0100 Rev.1.00

Page 6 of 16

Oct 07, 2013

AC Characteristics

±10%)

Test Conditions

• Input pulse levels: 0.4 V to 3.0 V

• Input rise and fall time: ≤ 5 ns

• Input timing reference levels: 0.8, 2.0 V

• Output load: 1TTL Gate +100 pF

• Output reference levels: 1.5 V, 1.5 V

Read Cycle

Parameter

Symbol

HN58C256API/AFPI/ATI

Unit

Test conditions

-85

-10

Min

Max

Min

Max

Address to output delay

—

85

—

100

ns

CE = OE = V

CE to output delay

—

85

—

100

ns

OE = V

OE to output delay

10

40

10

50

ns

CE = V

Address to output hold

0

—

0

—

ns

CE = OE = V

0

40

0

40

ns

CE = V

Write Cycle

Parameter

Symbol

Min*

2

Typ

Max

Unit

Test conditions

Address setup time

0

—

—

ns

Address hold time

50

—

—

ns

CE to write setup time (WE controlled)

0

—

—

ns

CE hold time (WE controlled)

0

—

—

ns

WE to write setup time (CE controlled)

0

—

—

ns

WE hold time (CE controlled)

0

—

—

ns

OE to write setup time

0

—

—

ns

OE hold time

0

—

—

ns

Data setup time

50

—

—

ns

Data hold time

0

—

—

ns

WE pulse width (WE controlled)

100

—

—

ns

CE pulse width (CE controlled)

100

—

—

ns

Data latch time

50

—

—

ns

Byte load cycle

0.2

—

30

μs

Byte load window

100

—

—

μs

Write cycle time

—

—

10*

3

ms

Time to device busy

120

—

—

ns

Write start time

0*

4

—

—

ns

driven.

2. Use this device in longer cycle than this value.

the internal write operation within this value.

5. A6 through A14 are page address and these addresses are latched at the first falling edge of

WE.

6. A6 through A14 are page address and these addresses are latched at the first falling edge of

CE.

7. See AC read characteristics.