HN58C256AI Series

R10DS0218EJ0100 Rev.1.00

Page 13 of 16

Oct 07, 2013

and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM

must be kept in an unprogrammable state while the CPU is in an unstable state.

Note: The EEPROM shoud be kept in unprogrammable state during VCC on/off by using CPU RESET signal.

CPU

RESET

Unprogrammable

Unprogrammable

*

*

2.1 Protection by

CE, OE, WE

To realize the unprogrammable state, the input level of control pins must be held as shown in the table below.

CE

×

×

OE

×

×

WE

×

×

×: Don’t care

3. Software data protection

To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is

enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is input.

To program data in the SDP enable mode, 3 bytes code must be input before write data.

Data

AA

↓

55

↓

A0

↓

Write data } Normal data input

Address

5555

↓

2AAA

↓

5555

↓

Write address

The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP disable

cycle, data can not be written.

Data

AA

↓

55

↓

80

↓

AA

↓

55

↓

20

Address

5555

↓

2AAA

↓

5555

↓

5555

↓

2AAA

↓

5555

The software data protection is not enabled at the shipment.

Note: There are some differences between Renesas Electronics' and other company’s for enable/disable sequence of

software data protection. If there are any questions, please contact with Renesas Electronics' sales offices.