AD7450ARMZ datasheet(17/22 Pages) AD

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AD7450

–17–

THREE-STATE

SDATA

SCLK

Figure 22. Entering Power-Down Mode

Once

CS has been brought high in this window of SCLKs, the

part will enter power-down, the conversion that was initiated by

the falling edge of

CS will be terminated, and SDATA will go

back into three-state. The time from the rising edge of

CS to

SDATA three-state enabled will never be greater than t8 (see

Timing Specifications). If

CS is brought high before the second

SCLK falling edge, the part will remain in normal mode and will

not power down. This will avoid accidental power-down due to

glitches on the

CS line.

To exit this mode of operation and power the AD7450 up again,

a dummy conversion is performed. On the falling edge of

CS, the

device will begin to power up and continue to power up as long

CS is held low until after the falling edge of the 10th SCLK. The

device will be fully powered up after 1

µs has elapsed and, as

shown in Figure 23, valid data will result from the next conversion.

CS is brought high before the 10th falling edge of SCLK, the

AD7450 will again go back into power-down. This avoids

accidental power-up due to glitches on the

CS line or an

inadvertent burst of eight SCLK cycles while

CS is low. So although

the device may begin to power up on the falling edge of

CS, it will

again power down on the rising edge of

CS as long as it occurs

before the 10th SCLK falling edge.

Power-Up Time

The power-up time of the AD7450 is typically 1

µs, which means

that with any frequency of SCLK up to 18 MHz, one dummy cycle

will always be sufficient to allow the device to power up. Once

the dummy cycle is complete, the ADC will be fully powered up

and the input signal will be acquired properly. The quiet time,

tQUIET, must still be allowed from the point at which the bus

goes back into three-state after the dummy conversion to the

next falling edge of

CS.

When running at the maximum throughput rate of 1 MSPS,

the AD7450 will power up and acquire a signal within

±0.5 LSB

in one dummy cycle, i.e., 1

µs. When powering up from the

power-down mode with a dummy cycle, as in Figure 23, the

track-and-hold, which was in hold mode while the part was

powered down, returns to track mode after the first SCLK

edge the part receives after the falling edge of

CS. This is shown

as Point A in Figure 23.

Although at any SCLK frequency one dummy cycle is sufficient

to power the device up and acquire VIN, it does not necessarily

mean that a full dummy cycle of 16 SCLKs must always elapse

to power up the device and acquire VIN fully; 1

µs will be

sufficient to power the device up and acquire the input signal.

For example, if a 5 MHz SCLK frequency was applied to the ADC,

the cycle time would be 3.2

µs (i.e., 1/(5 MHz)

16). In one

dummy cycle, 3.2

µs, the part would be powered up and VIN

acquired fully. However, after 1

µs with a 5 MHz SCLK, only

5 SCLK cycles would have elapsed. At this stage, the ADC would

be fully powered up and the signal acquired. So, in this case, the

CS can be brought high after the 10th SCLK falling edge and

brought low again after a time, tQUIET, to initiate the conversion.

When power supplies are first applied to the AD7450, the ADC

may either power up in the power-down mode or normal mode.

Because of this, it is best to allow a dummy cycle to elapse to

ensure the part is fully powered up before attempting a valid

conversion. Likewise, if the user wishes the part to power up in

power-down mode, then the dummy cycle may be used to ensure

the device is in power-down by executing a cycle such as that

shown in Figure 22.

Once supplies are applied to the AD7450, the power-up time is

the same as that when powering up from the power-down mode.

It takes approximately 1

µs to power up fully if the part powers

up in normal mode. It is not necessary to wait 1

µs before

executing a dummy cycle to ensure the desired mode of operation.

Instead, the dummy cycle can occur directly after power is

supplied to the ADC. If the first valid conversion is then performed

directly after the dummy conversion, care must be taken to ensure

that adequate acquisition time has been allowed.

As mentioned earlier, when powering up from the power-down

mode, the part will return to track upon the first SCLK edge

applied after the falling edge of

CS. However, when the ADC

powers up initially after supplies are applied, the track-and-hold

will already be in track. This means if (assuming one has the

facility to monitor the ADC supply current) the ADC powers

up in the desired mode of operation, and thus a dummy cycle is

not required to change the mode, then a dummy cycle is not

required to place the track-and-hold into track.

SDATA

INVALID DATA

SCLK

116

VALID DATA

THE PART BEGINS

TO POWER UP

THE PART IS FULLY POWERED

UP WITH V IN FULLY ACQUIRED

POWER-UP

Figure 23. Exiting Power-Down Mode

Rev. A

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