AD7450ARMZ datasheet(19/22 Pages) AD

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AD7450

–19–

AD7450 to TMS320C5x/C54x

The serial interface on the TMS320C5x/C54x uses a continuous

serial clock and frame synchronization signals to synchronize the

data transfer operations with peripheral devices, such as the

AD7450. The

CS input allows easy interfacing between the

TMS320C5x/C54x and the AD7450 with no glue logic required.

The serial port of the TMS320C5x/C54x is set up to operate in

burst mode with internal CLKX (Tx serial clock) and FSX (Tx

frame sync). The serial port control register (SPC) must have

the following setup: FO = 0, FSM = 1, MCM = 1, and

TXM = 1. The format bit, FO, may be set to 1 to set the word

length to 8 bits in order to implement the power-down mode on

the AD7450. The connection diagram is shown in Figure 26. For

signal processing applications, it is imperative that the frame

synchronization signal from the TMS320C5x/C54x provide equi-

distant sampling.

FSR

FSX

SCLK

CLKR

CLKX

*ADDITIONAL PINS OMITTED FOR CLARITY

AD7450*

TMS320C5x/C54x

SDATA

Figure 26. Interfacing to the TMS320C5x/C54x

AD7450 to MC68HC16

The serial peripheral interface (SPI) on the MC68HC16 is configured

for master mode (MSTR) = 1, clock polarity bit (CPOL) = 1,

and clock phase bit (CPHA) = 0. The SPI is configured by

writing to the SPI control register (SPCR)—see the 68HC16 user

manual. The serial transfer will take place as a 16-bit operation

when the SIZE bit in the SPCR register is set to SIZE = 1.

To implement the power-down modes with an 8-bit transfer set

SIZE = 0. A connection diagram is shown in Figure 27.

SS/PMC3

SCLK

SCLK/PMC2

*ADDITIONAL PINS OMITTED FOR CLARITY

AD7450*

MC68HC16

SDATA

MISO/PMC0

Figure 27. Interfacing to the MC68HC16

AD7450 to DSP56xxx

The connection diagram in Figure 28 shows how the AD7450 can

be connected to the SSI (synchronous serial interface) of the

DSP56xxx family of DSPs from Motorola. The SSI is operated

in synchronous mode (SYN bit in CRB = 1) with internally

generated 1-bit clock period frame sync for both Tx and Rx

(Bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word length to

16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To imple-

ment the power-down mode on the AD7450, the word length

can be changed to 8 bits by setting its WL1 = 0 and WL0 = 0 in

CRA. It should be noted that for signal processing applica-

tions, it is imperative that the frame synchronization signal

from the DSP56xxx will provide equidistant sampling.

SR2

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

AD7450*

DSP56xxx

SDATA

SRD

Figure 28. Interfacing to the DSP56xxx

APPLICATION HINTS

Grounding and Layout

The printed circuit board that houses the AD7450 should be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes that can be easily separated. A minimum

etch technique is generally best for ground planes since it gives

the best shielding. Digital and analog ground planes should be

joined in only one place, and the connection should be a star

ground point established as close to the GND pin on the AD7450

as possible. Avoid running digital lines under the device, as this

will couple noise onto the die. The analog ground plane should

be allowed to run under the AD7450 to avoid noise coupling.

The power supply lines to the AD7450 should use as large a trace

as possible to provide low impedance paths and reduce the effects

of glitches on the power supply line.

Fast switching signals, such as clocks, should be shielded with

digital ground to avoid radiating noise to other sections of the

board, and clock signals should never run near the analog

inputs. Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to each

other. This reduces the effects of feedthrough through the

board. A microstrip technique is by far the best but is not

always possible with a double-sided board.

In this technique, the component side of the board is dedicated

to ground planes, while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should

be decoupled with 10

µF tantalum capacitors in parallel with

0.1

µF capacitors to GND. To achieve the best from these

decoupling components, they must be placed as close as possible

to the device.

Rev. A

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