MPC8548ECPXATHC datasheet(34/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC)

Figure 13 shows the MII receive AC timing diagram.

Figure 13. MII Receive AC Timing Diagram

8.2.4

TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

8.2.4.1

TBI Transmit AC Timing Specifications

This table provides the TBI transmit AC timing specifications.

Table 30. TBI Transmit AC Timing Specifications

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

TCG[9:0] setup time GTX_CLK going high

tTTKHDV

2.0

—

TCG[9:0] hold time from GTX_CLK going high

tTTKHDX

1.0

—

GTX_CLK rise (20%–80%)

tTTXR

——

1.0

GTX_CLK fall time (80%–20%)

tTTXF

——

1.0

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI

transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid

state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high

(H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript

of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. Guaranteed by design.

RX_CLK

RXD[3:0]

tMRDXKL

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

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