MPC8548ECPXATHC datasheet(53/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

Programmable Interrupt Controller

In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed

polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods).

12 JTAG

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of

the device.

12.1

JTAG DC Electrical Characteristics

This table provides the DC electrical characteristics for the JTAG interface.

12.2

JTAG AC Electrical Specifications

This table provides the JTAG AC timing specifications as defined in Figure 30 through Figure 32.

Table 43. JTAG DC Electrical Characteristics

Parameter

Symbol1

Min

Max

Unit

High-level input voltage

VIH

2OVDD + 0.3

Low-level input voltage

VIL

–0.3

0.8

Input current (VIN

1 = 0 V or V

IN = VDD)IIN

—±5

A

High-level output voltage (OVDD = min, IOH = –2 mA)

VOH

2.4

—

Low-level output voltage (OVDD = min, IOL = 2 mA)

VOL

—0.4

Note:

1. Note that the symbol VIN, in this case, represents the OVIN.

Table 44. JTAG AC Timing Specifications (Independent of SYSCLK)1

Parameter

Symbol2

Min

Max

Unit

Notes

JTAG external clock frequency of operation

fJTG

033.3

MHz

—

JTAG external clock cycle time

t JTG

—

JTAG external clock pulse width measured at 1.4 V

tJTKHKL

—

JTAG external clock rise and fall times

tJTGR & tJTGF

TRST assert time

tTRST

—

Input setup times:

Boundary-scan data

TMS, TDI

tJTDVKH

tJTIVKH

—

Input hold times:

Boundary-scan data

TMS, TDI

tJTDXKH

tJTIXKH

—

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