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0

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© 2012 Exar Corporation

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Rev. 1.2.2

GPIO Pins Polarity

The polarity of the GPIO pin can be set by using the GPIO_ACT_POL register. This register allows

any GPIO pin whether configured as an input or output to change polarity. Bits [5:0] are used to

[5:4] are ignored.

Supply Rail Enable

Each GPIO can be configured to enable a specific power rail for the system. The GPIOx_CFG

register allows a GPIO to enable/disable any of the following rails controlled by the chip:

•

A single buck power controller

•

The Standby LDO

•

Any mix of the Standby LDO and power controller(s)

When the configured GPIO is asserted externally, the corresponding rails will be enabled, and they

will be similarly disabled when the GPIO is de-asserted. This supply enabling/disabling can also be

Power Good Indicator

The GPIO pins can be configured as Power Good indicators for one or more rails. The GPIO pin is

asserted when all rails configured for this specific IO are within specified limits for regulation. This

information can also be found in the READ_PWRGD_SS_FLAG status register.

Fault and Warning Indication

The GPIOs can be configured to signal Fault or Warning conditions when they occur in the chip.

Each GPIO can be configured to signal one of the following:

•

OCP Fault on Channel 1 - 4

•

OCP Warning on Channel 1 - 4

•

OVP Fault on Channel 1 - 4

•

UVLO Fault on VIN1 or VIN2

•

UVLO Warning on VIN1 or VIN2

•

Over Temperature Fault or Warning

This interface allows for the full control, monitoring, and reconfiguration of the semiconductor.

MSB

6

5

4

3

2

1

0

R/W

LSB

Fig. 29: Alignment of I2C address in 8 bit byte

There is one address byte required since 7-bit addresses are used. The last bit of the address byte

address is stored in the NVM. One can program a blank device with the 7-bit Slave address or

select one of the preprogrammed options. The 7-bit address plus the R/W bit create an 8-bit data

value that is sent on the bus.