X

0

Q

© 2012 Exar Corporation

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Rev. 1.2.2

PIN ASSIGNMENT

30

29

28

27

26

25

24

23

21

22

10

1

2

3

4

5

6

7

8

9

AVDD

DVDD

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4_SDA

GPIO5_SCL

ENABLE

GL2

LX2

GH2

BST2

VCCD

BST4

GH4

LX4

GL4

PGND4

DGND

Exposed Pad: AGND

XRP7708

XRP7740

TQFN

6mm X 6mm

Fig. 3: XRP7708/40 Pin Assignment

PIN DESCRIPTION

Name

Pin Number

Description

VIN1

39

Power source for the internal linear regulators to generate VCCA, VDD and the Standby

LDO (LDOOUT). Place a decoupling capacitor close to the controller IC. Also used in

UVLO1 fault generation – if VIN1 falls below the user programmed limit, all channels are

shut down. The VIN1 pin needs to be tied to VIN2 on the board with a short trace.

VIN2

38

If the Vin2 pin voltage falls below the user programmed UVLO VIN2 level all channels are

shut down. The VIN2 pin needs to be tied to VIN1 on the board with a short trace.

VCCA

37

Output of the internal 5V LDO. This voltage is internally used to power analog blocks. This

pin should be bypassed with a minimum of 4.7uF to AGND

VCCD

26

Gate Drive input voltage. This is not an output voltage. This pin can be connected to

VCCA to provide power for the Gate Drive. VCCD should be connected to VCCA with the

shortest possible trace and decouple with a minimum 1µF capacitor. Alternatively, VCCD

could be connected to an external supply (not greater than 5V).

PGND1- PGND4

36,31,16,21

GL return connection. Ground connection for the low side gate driver. Connect at low side

FET source. Connecting to the ground plane at the chip will inject noise into the local

AVDD

1

Output of the internal 1.8V LDO. A decoupling capacitor should be placed between AVDD

and AGND close to the chip (with short traces).

DVDD

2

Input for powering the internal digital logic. This pin should be connected to AVDD.