40

Am29BDS323D

P R E L I M INARY

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

programming typicals assume checkerboard pattern.

3. The typical chip programming time is considerably less than the maximum chip programming time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 4 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1 million cycles.

DATA RETENTION

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

32 Kword

1.5

15

s

Excludes 00h programming

prior to erasure (Note 4)

4 Kword

0.3

5

Chip Erase Time

97

s

Word Programming Time

11.5

360

µs

Excludes system level

overhead (Note 5)

Accelerated Word Programming Time

4

210

µs

Chip Programming Time (Note 3)

24

72

s

Excludes system level

overhead (Note 5)

Accelerated Chip Programming Time

8

24

s

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

°C10

Years

125

°C20

Years