AM29BDS323D datasheet(17/44 Pages) AMD

17 / 44 page

Am29BDS323D

P R E L I M INARY

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass rese t

command sequence. The first cycle must contain the

bank address and the data 90h. The second cycle

need only contain the data 00h. The bank then returns

to the read mode.

The device offers accelerated program operations

through VPP. When the system asserts VID on this

input, the device automatically enters the Unlock

Bypass mode. The system may then write the

two- cy cle Unloc k Bypas s pr og r a m comman d

sequence. The device uses the higher voltage on the

VPP input to accelerate the operation. Note that sectors

must be unlocked using the Sector Lock/Unlock

command sequence prior to raising VPP to VID.

Figure 1 illustrates the algorithm for the program oper-

ation. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters, and

Figure 12 for timing diagrams.

Figure 1.

Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations.

The host system may also initiate the chip erase

command sequence while the device is in the unlock

bypass mode. The command sequence is two cycles

cycles in length instead of six cycles. Table 4 shows the

address and data requirements for the chip erase

command sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7 or DQ6/DQ2.

Refer to the Write Operation Status section for infor-

mation on these status bits.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset

immediately terminates the erase operation. If that

occurs, the chip erase command sequence should be

reinitiated once that bank has returned to reading array

data, to ensure data integrity.

Figure 2 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters, and

Figure 13 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 4 shows the address

and data requirements for the sector erase command

sequence.

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

After the command sequence is written, a sector erase

time-out of no less than 50 µs occurs. During the

time-out period, additional sector addresses and sector

erase commands may be written. Loading the sector

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Note: See Table 4 for program command sequence.

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