AM79C970A datasheet(93/219 Pages) AMD

93 / 219 page

P R E L I M I N A R Y

AMD

Am79C970A

controller from claiming any memory cycles not in-

tended for it.

The Expansion ROM interface uses some of the same

pins as the GPSI interface. Simultaneous use of both

functions is not possible. Reading from the Expansion

ROM and then reconfiguring the pins to the GPSI mode

is supported. An external transceiver is required to pre-

vent contention between the GPSI signals and the data

outputs from the Expansion ROM.

EROE can be used

as control signal for the external transceiver.

After an H_RESET all pins are internally configured to

function as Expansion ROM interface. When the GPSI

interface is selected by setting PORTSEL (CSR15, bits

8–7) to 10b, the PCnet-PCI II controller will terminate

all further read accesses to Expansion ROM by assert-

ing

TRDY within two clock cycles. The read data will

be undefined.

During the boot procedure the system will try to find an

Expansion ROM. A PCI system assumes that an

Expansion ROM is present when it reads the ROM sig-

nature 55h (byte 0) and AAh (byte 1). A design without

Expansion ROM can guarantee that the Expansion

ROM detection fails by connecting two adjacent ERD

pins together and tying them high or low.

EEPROM Microwire Interface

The PCnet-PCI II controller contains a built-in capability

for reading and writing to an external serial EEPROM.

This built-in capability consists of an interface for direct

connection to a Microwire compatible EEPROM, an

automatic EEPROM read feature, and a user-program-

mable register that allows direct access to the Microwire

interface pins.

Automatic EEPROM Read Operation

Shortly after the deassertion of the

RST pin, the

PCnet-PCI II controller will read the contents of the

EEPROM that is attached to the Microwire interface.

Because of this automaticread capability of the PCnet-

PCI II controller, an EEPROM can be used to program

many of the features of the PCnet-PCI II controller at

power-up, allowing system-dependent configuration in-

formation to be stored in the hardware, instead of inside

the device driver.

If an EEPROM exists on the Microwire interface, the

PCnet-PCI II controller will read the EEPROM contents

at the end of the H_RESET operation. The EEPROM

contents will be serially shifted into a temporary register

and then sent to various register locations on board the

PCnet-PCI II controller. Access to the PCnet-PCI II con-

troller configuration space, the Expansion ROM or any

I/O resource is not possible during the EEPROM read

operation. The PCnet-PCI II controller will terminate any

access attempt with the assertion of

DEVSEL and

STOP while TRDY is not asserted, signaling to the initia-

tor to disconnect and retry the access at a later time.

A checksum verification is performed on the data that is

read from the EEPROM. If the checksum verification

passes, PVALID (BCR19, bit 15) will be set to ONE. If

the checksum verification of the EEPROM data fails,

PVALID will be cleared to ZERO and the PCnet-PCI II

controller will force all EEPROM-programmable BCR

registers back to their H_RESET default values. The

content of the Address PROM locations (offsets 0h–Fh

from the I/O or memory mapped I/O base address),

however, will not be cleared. The 8 bit checksum for the

entire 36 bytes of the EEPROM should be FFh.

If no EEPROM is present at the time of the automatic

read operation, the PCnet-PCI II controller will recog-

nize this condition and will abort the automatic read op-

eration and clear both the PREAD and PVALID bits in

BCR19. All EEPROM-programmable BCR registers will

be assigned their default values after H_RESET. The

content of the Address PROM locations (offsets 0h–Fh

from the I/O or memory mapped I/O base address) will

be undefined.

If the user wishes to modify any of the configuration bits

that are contained in the EEPROM, then the seven com-

mand, data and status bits of BCR19 can be used to

write to the EEPROM. After writing to the EEPROM, the

host should set the PREAD bit of BCR19. This action

forces a PCnet-PCI II controller re-read of the EEPROM

so that the new EEPROM contents will be loaded into

the EEPROM-programmable registers on board the

PCnet-PCI II controller. (The EEPROM-programmable

registers may also be reprogrammed directly, but only

information that is stored in the EEPROM will be pre-

served at system power-down.) When the PREAD bit of

BCR19 is set, it will cause the PCnet-PCI II controller to

ignore further accesses to the PCnet-PCI II controller

configuration space, the Expansion ROM, or any I/O re-

source until the completion of the EEPROM read opera-

tion. The PCnet-PCI II controller will terminate these

access attempts with the assertion of

DEVSEL and

STOP while TRDY is not asserted, signaling to the initia-

tor

disconnect

and

retry

the

access

later time.

EEPROM Auto-Detection

The PCnet-PCI II controller uses the EESK/

LED1/SFBD

pin to determine if an EEPROM is present in the system.

At the rising edge of CLK during the last clock during

which

RST is asserted, the PCnet-PCI II controller will

sample the value of the EESK/

LED1/SFBD pin. If the

sampled value is a ONE, then the PCnet-PCI II control-

ler assumes that an EEPROM is present, and the

EEPROM read operation begins shortly after the

RST

deasserted.

the

sampled

value

EESK/

LED1/SFBD is a ZERO, the PCnet-PCI II

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