AM79C972BVCW datasheet(87/130 Pages) AMD

87 / 130 page

Am79C972

Figure 49.

Pattern Match RAM

There are two general methods to place the PCnet-

FAST+ into the Magic Packet mode. The first is the soft-

ware method. In this method, either the BIOS or other

software, sets the MPMODE bit (CSR5, bit 1). Then

PCnet-FAST+ controller must be put into suspend

mode (see description of CSR5, bit 0), allowing any

current network activity to finish. Finally, either PG must

be deasserted (hardware control) or MPEN (CSR5, bit

2) must be set to 1 (software control).

Note: FASTSPNDE (CSR7, bit 15) has no meaning in

Magic Packet mode.

The second method is the hardware method. In this

method, the MPPEN bit (CSR116, bit 4) is set at power

up by the loading of the EEPROM. This bit can also be

set by software. The PCnet-FAST+ will be placed in the

Magic Packet Mode when either the PG input is

deasserted or the MPEN bit is set. WUMI output will be

asserted when the PCnet-FAST+ is in the Magic

Packet mode. Magic Packet mode can be disabled at

any time by asserting PG or clearing MPEN bit.

When the PCnet-FAST+ controller detects a Magic

Packet frame, it sets the MPMAT bit (CSR116, bit 5),

the MPINT bit (CSR5, bit 4), and the PME_STATUS bit

(PMCSR, bit 15). The setting of the MPMAT bit will also

cause the RWU pin to be asserted and if the PME_EN

or the PME_EN_OVR bits are set, then the PME will be

asserted as well. If IENA (CSR0, bit 6) and MPINTE

(CSR5, bit 3) are set to 1, INTA will be asserted. Any

one of the four LED pins can be programmed to indi-

cate that a Magic Packet frame has been received.

BCR 47

BCR 46

BCR 45

BCR Bit Number 15

0 15

PMR_B4

PMR_B3

PMR_B2

PMR_B1

PMR_B0

Pattern Match

RAM Address

Pattern Match RAM Bit Number

Comments

P3 pointer

P2 pointer

P1 pointer

P0 pointer

Pattern Enable

bits

First Address

P7 pointer

P6 pointer

P5 pointer

P4 pointer

Second

Address

Data Byte 3

Data Byte 2

Data Byte1

Data Byte 0

Pattern Control

Start Pattern

2+n

Data Byte 4n+3

Date Byte 4n+2

Data Byte 4n+1

Data Byte 4n+0

Pattern Control

End Pattern P1

Data Byte 3

Data Byte 2

Data Byte 1

Data Byte 0

Pattern Control

Start Pattern Pk

J+m

Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0

Pattern Control

End Pattern Pk

Last Address

EOP

SKIP

MASK

21485C-52

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