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Input Clock

Analog

Input

Signal

Sample

N

N + 1

N + 2

N + 3

N + 4

N + 1 4

N + 1 6

N + 1 7

N + 1 5

N − 17

N − 16

N − 15

N − 14

N − 13

N − 3

N − 2

N − 1

N

Data Out

(D0−D11)

17.5 Clock Cycles

Data Invalid

Output Clock

TIMING CHARACTERISTICS

(1)

ADS5522

SBAS320C – MAY 2004 – REVISED FEBRUARY 2007

NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above

timing matches closely with the specified values.

Figure 1. Timing Diagram

Typical values given at T

AV

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Switching Specification

Aperture delay

Input CLK falling edge to data sampling point

1

ns

Aperture jitter (uncertainty)

Uncertainty in sampling instant

300

fs

Data setup time

3.6

4.7

ns

Data hold time

50% of CLKOUT rising edge to data becoming

1.8

3.1

ns

Input clock to output data valid

Input clock rising edge to data valid start delay

3.3

5.0

ns

Input clock to output data valid

Input clock rising edge to data valid end delay

8.4

11.1

ns

Output clock jitter

Uncertainty in CLKOUT rising edge, peak-to-peak

210

315

ps

Output clock rise time

Rise time of CLKOUT measured from 20% to 80%

2.5

2.8

ns

Output clock fall time

Fall time of CLKOUT measured from 80% to 20%

2.1

2.3

ns

Input clock to output clock delay

Input clock rising edge zero crossing, to output

7.1

8

8.9

ns

clock rising edge 50%

Data rise time

Data rise time measured from 20% to 80% of

5.6

6.1

ns

Data fall time

Data fall time measured from 80% to 20% of

4.4

5.1

ns

Output enable(OE) to data output

Time required for outputs to have stable timings

1000

Clock

delay

cycles

(1)

Timing parameters are ensured by design and characterization, and not tested in production.

(2)

See Table 5 through Table 6 in the Application Information section for timing information at additional sampling frequencies.

(3)

Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.

(4)

See the Output Information section for details on using the input clock for data capture.

(5)

These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 2). Add 1/2 clock period for the valid

number for a falling edge CLKOUT polarity.

(6)

Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect

to input clock.

6

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