DAC5687IPZP datasheet(33/79 Pages) TI

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R/W

t(SCLKL)

SDENB

SCLK

SDIO

N1 N0

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SDENB

SCLK

SDIO

Instruction Cycle

Data Transfer Cycle(s)

ts(SDENB)

t(SCLK)

th(SDIO)

ts(SDIO)

t(SCLKH)

T0037-02

R/W

SDENB

SCLK

SDIO

N1 N0 A4 A3 A2 A1 A0

D6 D5 D4 D3 D2

D0 0

Instruction Cycle

Data Transfer Cycle(s)

SDO

D7 D6 D5 D4 D3 D2 D1 D0 0

3-Pin Configuration

Output

4-Pin Configuration

Output

SDENB

SCLK

SDIO

Data n

Data n−1

SDO

td(DATA)

T0038-02

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

Figure 33. Serial-Interface Write Timing Diagram

Figure 34 shows the serial interface timing diagram for a DAC5687 read operation. SCLK is the serial interface

clock input to the DAC5687. Serial data enable SDENB is an active-low input to the DAC5687. SDIO is serial

data in during the instruction cycle. In three-pin configuration, SDIO is data out from the DAC5687 during the

data transfer cycle(s), while SDO is in a high-impedance state. In four-pin configuration, SDO is data out from the

DAC5687 during the data transfer cycle(s). At the end of the data transfer, SDO outputs low on the final falling

edge of SCLK until the rising edge of SDENB, when it goes into the high-impedance state.

Figure 34. Serial-Interface Read Timing Diagram

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