DAC5687IPZP datasheet(40/79 Pages) TI

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daca_offset

{–4096, –4095, ..., 4095}

B0165−01

dacb_offset

{–4096, –4095, ..., 4095}

Analog DAC Gain

fullscale +

16 V

extio

BIAS

GAINCODE ) 1

B 1 *

FINEGAIN

3072

Clock Modes

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

During the four DAC clock cycles, the partially updated offset register values are summed to the DAC signal.

This can result in offset values during the first three DAC clock cycles that are significantly different from the

starting and ending offset values. For example, Table 11 shows the transition from offset value 1023 to 1025.

The bit changes in each clock cycle are in bold. As can be seen, the transition between 1023 and 1025 results in

offset values of 1023, 1279, and 1039 during the transition.

Table 11. Offset Values During Transition

DAC Clock Cycle

Signed Integer Value

Binary Format

Hexadecimal Format

1023 starting value

00 0011 1111 1111

0x03FF

1023

00 0011 1111 1111

0x03FF

1279

00 0100 1111 1111

0x04FF

1039

00 0100 0000 1111

0x040F

1025 ending value

00 0100 0000 0001

0x0401

Figure 42. DAC Offset Block

The full-scale DAC output current can be set by programming the daca_gain and dacb_gain registers. The DAC

gain value controls the full-scale output current.

where GAINCODE = daca_gain(11:8) or dacb_gain(11:8) is the coarse gain setting (0 to 15) and FINEGAIN =

daca_gain(7:0) or dacb_gain(7:0) (–128 to 127) is the fine gain setting.

In the DAC5687, the internal clocks (1

×, 2×, 4×, and 8× as needed) for the logic, FIR interpolation filters, and

DAC are derived from a clock at either the input data rate using an internal PLL (PLL clock mode) or DAC output

sample rate (external clock mode). Power for the internal PLL blocks (PLLVDD and PLLGND) are separate from

the other clock generation blocks power (CLKVDD and CLKGND), thus minimizing phase noise within the PLL.

The DAC5687 has three clock modes for generating the internal clocks (1

×, 2×, 4×, and 8× as needed) for the

logic, FIR interpolation filters, and DACs. The clock mode is set using the PLLVDD pin and dual_clk in register

CONFIG1.

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