Rev 2.6, August 1, 2010

Page 2 of 8

SL16010DC

Pin Configuration

10

9

8

7

1

2

3

4

XOUT

REFCLK

VDD2

SSEL0

XIN/CLKIN

VSS2

SSEL1

VDD1

SSCLK

5

6

VSS1

Figure 2. 10-Pin TDFN (3x3x0.75 mm)

Table 1. Pin Description

Pin

Number

Pin Name

Pin Type

Pin Description

1

XIN/CLKIN

Input

External crystal or clock input. Capacitance at this pin is 4 pF-typ.

2

VSS2

Power

Power supply ground for 27.000MHz REFCLK output.

3

SSEL1

Input

SSEL1 spread percent selection pin. Refer to Table 5 for available

spread options using SSEL1 pin. Three state, Low (L), Middle (M) and

High (H) digital input logic levels. This pin has 150k

Ω-typ input pull down

resistor.

4

VDD1

Power

Positive power supply for 100.000MHz SSCLK output. 3.3V +/-10%.

5

SSCLK

Output

SSCLK clock output. 100.000MHz nominal. Refer to Table 5 for available

spread % options by using SSEL0 and SSEL1 control pins.

6

VSS1

Power

Power supply ground for 100.000MHz SSCLK output.

7

SSEL0

Input

SSEL spread percent selection pin. Refer to Table 5 for available

spread options using SSEL0 pin. Three state, Low (L), Middle (M) and

High (H) digital input logic levels. This pin has 150k

Ω-typ input pull down

resistor.

8

VDD2

Power

Positive power supply for 27.000MHz REFCLK output. 3.3V +/-10%.

9

REFCLK

Output

REFCLK clock output. 27.000MHz nominal.

10

XOUT

Output

Crystal output. Capacitance at this pin 4 pF-typ. If clock input is used,

leave this pin not connected (N/C).