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LTC1325CSW Datasheet(PDF) 13 Page - Linear Technology |
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LTC1325CSW Datasheet(HTML) 13 Page - Linear Technology |
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13 / 24 page ![]() 13 LTC1325 FUNCTIONAL DESCRIPTIO The chip enters the discharge mode when the proper mode command bits are set and the power shutdown command bit is clear. If a fault condition does not exist, then the DIS pin is pulled up to VDD by the internal driver. The DIS voltage is used to turn on an external transistor which discharges the battery through an external series resistor RDIS. Discharging will continue until a new command word is input to change the mode or a fault condition occurs. Charge Mode Command: MOD1 = 1, MOD0 = 0, PS = 0 Status: BATP = 1, BATR = 0, FMCV = 0, FEDV = X, FHTF = 0, FLTF = 0, tOUT = 0 The chip enters the charge mode when the proper mode command bits are set and the power shutdown command bit is clear. If a fault condition does not exist then charging can begin. Charging will continue until a new command word is input to change the mode or a fault condition occurs. The charge current may be regulated by a programmable 111kHz PWM buck current regulator, or by using the PFET to gate an external current regulator or current limited transformer. 111kHz PWM Controller The block diagram of the charging loop connected as a PWM buck current regulator is shown in Figure 4. The PWM may operate in either continuous or discontinuous mode. The loop forces the average voltage across the sense resistor to be equal to the voltage at the output of the DAC, so that the charging current becomes VDAC/RSENSE. With switch S2 on and the others off, amplifier A1 along with C1, R1 and R2 are configured as an integrator with 16kHz bandwidth. The output of the integrator is the average difference between the voltage across the sense resistor and the DAC output voltage. The rising edge of the oscillator waveform triggers the one shot which sets the flip-flop output high. This turns on the external PFET P1 by pulling its gate low via the FET driver. With P1 on, the current through the inductor L1 starts to (MCV), minimum cell voltage exceeded (EDV), high tem- perature limit exceeded (HTF), low temperature limit ex- ceeded (LTF) and time limit exceeded (tOUT). When a fault condition occurs, the discharge and charge loops are disabled or prevented from turning on and the fail-safe bit (FS) is set. The chip is reset by shifting in a new command word with the fail-safe clear FSCLR bit set. The 8-bit status word contains the state of each fault condition. Power Shutdown Mode Command: MOD1 = X, MOD0 = X, PS = 1 Status: BATP = X, BATR = X, FMCV = X, FEDV = X, FHTF = X, FLTF = X, tOUT = X In the power shutdown mode, the analog section is turned off and the supply current drops to 30 µA. The voltage regulator, which provides power to the internal analog circuitry and external bias networks, is shut down. The voltage divider across the battery is disconnected and the only circuit left on is the voltage regulator for the serial interface logic. Idle Mode Command: MOD1 = 0, MOD0 = 0, PS = 0 Status: BATP = X, BATR = X, FMCV = X, FEDV = X, FHTF = X, FLTF = X, tOUT = X The chip enters the idle mode when the proper mode command bits are set and the power shutdown command bit is cleared. During the idle mode, the chip is fully powered, but the discharge, charge and gas gauge circuits are off. The chip may be placed in the idle mode momen- tarily while charging the battery, allowing an ADC mea- surement to be made without any switching noise from the PWM current source affecting the accuracy of the reading. The mode command bits are picked off as they appear at DIN, so that while the rest of the command word is being shifted in, the charging loop has time to settle before an ADC measurement is made. Discharge Mode Command: MOD1 = 0, MOD0 = 1, PS = 0 Status: BATP = 1, BATR = 0, FMCV = X, FEDV = 0, FHTF = 0, FLTF = 0, tOUT = 0 |
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