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LTC1325CSW Datasheet(PDF) 3 Page - Linear Technology |
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LTC1325CSW Datasheet(HTML) 3 Page - Linear Technology |
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3 / 24 page  3 LTC1325 VDD = 12V ±5%, TA = 25°C, unless otherwise noted. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS thDI Hold Time, DIN After CLK↑ 150 ns tdsuCS Setup Time, CS Before First CLK ↑ 1 µs tdsuDI Setup Time, DIN Stable Before First CLK↑ 400 ns tWHCLK CLK High Time 0.8 µs tWLCLK CLK Low Time 1 µs tWHCS CS High Time Between Data Transfers 1 µs tWLCS CS Low Time During Data Transfer MSBF = 1 43 CLK Cycles MSBF = 0 52 CLK Cycles RECO E DED CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to the GND pin. Note 3: VREG within specified min and max limits, CLK (Pin 5) = 500kHz, unless otherwise stated. ADC clock is the serial CLK. Note 4: Linearity error is specified between the actual end points of the A/D transfer curve. Note 5: Channel leakage is measured after channel selection. Note 6: Gas gauge offset excludes A/D offset error. Note 7: I = VDAC(Duty Ratio)/RSENSE, where VDAC is the DAC output voltage with control bits VR1 = VR0 = 1, duty ratio = 1 and RSENSE is determined by the user. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOL Output Low Voltage DOUT, IOUT = 1.6mA q 0.4 V VOH Output High Voltage DOUT, IOUT = – 1.6mA q 2.4 V IOZ Hi-Z Output Leakage VCS = 5V q ±10 µA VOHFET DIS or PGATE Output High VDD = 4.5V to 16V q VDD – 0.05 V VOLFET DIS or PGATE Output Low VDD = 4.5V to 16V q 0.05 V tdDO Delay Time, CLK ↓ to DOUT Valid See Test Circuits q 650 ns tdis Delay Time, CS ↑ to DOUT Hi-Z See Test Circuits q 510 ns ten Delay Time, CLK ↓ to DOUT Enabled See Test Circuits q 400 ns thDO Time DOUT Remains Valid After CLK↓ See Test Circuits q 30 ns trDOUT DOUT Rise Time See Test Circuits q 250 ns tfDOUT DOUT Fall Time See Test Circuits q 100 ns fCLK Serial I/O Clock Frequency CLK Pin q 25 500 kHz trPGATE PGATE Rise Time CLOAD = 1500pF q 150 ns tfPGATE PGATE Fall Time CLOAD = 1500pF q 150 ns fOSC Internal Oscillator Frequency Charge Mode, Fail-Safes Disabled 90 111 130 kHz A/D Converter Offset Error VIN Channel (Note 3) q ±2 LSB Linearity Error VIN Channel (Notes 3, 4) q ±0.5 LSB Full-Scale Error VIN Channel (Note 3) q ±1 LSB On-Channel Leakage VIN Channel ON Only (Notes 3, 5) q ±10 µA Off-Channel Leakage VIN Channel OFF (Notes 3, 5) q ±10 µA |
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