LTC1553LCSW datasheet(18/20 Pages) LINER

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LTC1553L

APPLICATIONS INFORMATION

capacitors shown at VCC and PVCC will help provide

optimum regulation performance.

5. The (+) plate of CIN should be connected as close as

possible to the drain of the upper MOSFET. An addi-

tional 1

µF ceramic capacitor between VIN and power

ground is recommended.

6. The SENSE pin is very sensitive to pickup from the

switching node. Care should be taken to isolate SENSE

from possible capacitive coupling to the inductor switch-

ing signal. A 0.1

µF is required between the SENSE pin

and the SGND pin next to the LTC1553L.

7. OUTEN is a high impedance input and should be

externally pulled up to a logic HIGH for normal

operation.

8. Kelvin sense IMAX and IFB at Q1 drain and source pins.

ground plane at a single point, preferably at a fairly quiet

point in the circuit such as close to the output capaci-

tors. This is not always practical, however, due to

physical constraints. Another reasonably good point to

make this connection is between the output capacitors

and the source connection of the low side FET Q2. Do

not tie this single point ground in the trace run between

the low side FET source and the input capacitor ground,

as this area of the ground plane will be very noisy.

3. The small signal resistors and capacitors for frequency

compensation and soft start should be located very

close to their respective pins and the ground ends

connected to the signal ground pin through a separate

trace. Do not connect these parts to the ground plane!

4. The VCC and PVCC decoupling capacitors should be as

close to the LTC1553L as possible. The 10

µF bypass

Figure 10. LTC1553L Layout Diagram

µF

5.6k

1153L F10

0.1

µF

SGND

OUTEN

VID0

VID1

VID2

VID3

VID4

PVCC

VCC

SENSE

0.1

µF

VOUT

PVCC

RIMAX

BOLD LINES INDICATE

HIGH CURRENT PATHS

CSS

COUT

CIN

VIN

5.6k

LTC1553L

RIFB

GND

IMAX

IFB

COMP

VID0

VID1

VID2

VID3

VID4

PWRGD

FAULT

0.1

µF

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