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UPD75P4308GS Datasheet(PDF) 39 Page - NEC

Part # UPD75P4308GS
Description  4-BIT SINGLE-CHIP MICROCONTROLLER
PDF  60 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD75P4308GS Datasheet(HTML) 39 Page - NEC

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µPD75P4308
39
Serial transfer operation
2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
tKCY1
VDD = 2.7 to 5.5 V
1300
ns
3800
ns
SCK high-, low-level
tKL1, tKH1
VDD = 2.7 to 5.5 V
tKCY1/2–50
ns
widths
tKCY1/2–150
ns
SINote 1 setup time (to SCK
↑)tSIK1
VDD = 2.7 to 5.5 V
150
ns
500
ns
SINote 1 hold time (from SCK
↑)tKSI1
VDD = 2.7 to 5.5 V
400
ns
600
ns
SCK
↓ → SONote 1 output
tKSO1
RL = 1 k
Ω,VDD = 2.7 to 5.5 V
0
250
ns
delay time
CL = 100 pFNote 2
0
1000
ns
Notes 1. In the 2-wire serial I/O mode, read SB0 instead.
2. RL and CL are the load resistance and load capacitance of the SO output line.
2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
tKCY2
VDD = 2.7 to 5.5 V
800
ns
3200
ns
SCK high-, low-level
tKL2, tKH2
VDD = 2.7 to 5.5 V
400
ns
widths
1600
ns
SINote 1 setup time (to SCK
↑)tSIK2
VDD = 2.7 to 5.5 V
100
ns
150
ns
SINote 1 hold time (from SCK
↑)tKSI2
VDD = 2.7 to 5.5 V
400
ns
600
ns
SCK
↓ → SONote 1 output
tKSO2
RL = 1 k
Ω,VDD = 2.7 to 5.5 V
0
300
ns
delay time
CL = 100 pFNote 2
0
1000
ns
Notes 1. In the 2-wire serial I/O mode, read SB0 instead.
2. RL and CL are the load resistance and load capacitance of the SO output line.



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