PCIe Gen2, 5.0 GT/s 8-lane 8-port PCI Express

Features

PEX 8608 General Features

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8-lane PCI Express switch

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Integrated 5.0 GT/s SerDes

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Up to 8 configurable ports

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15 x 15mm

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Typical Power: 1.39 Watts

PEX 8608 Key Features

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Standards Compliant

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PCI Express Base Specification r2.0

(Backwards compatible with PCIe

r1.0a/1.1)

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PCI Power Management Spec r1.2

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Microsoft Vista Compliant

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Supports Access Control Services

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Dynamic link-width control

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Dynamic SerDes Speed Control

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High Performance

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Non-blocking internal architecture

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Full line rate on all ports

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Cut-Thru latency: 130ns

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2KB max payload size

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Read Pacing

(intelligent bandwidth allocation)

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Dual Cast

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Dual-Host & Fail-Over Support

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Configurable Non-Transparent port

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Moveable upstream port

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Crosslink port capability

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Flexible Configuration

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8 flexible & configurable ports

(x1 or x4)

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Configurable with strapping pins,

EEPROM, I

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Lane and polarity reversal

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PCI Express Power Management

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Link power management states: L0, L0s,

L1, L2/L3 Ready, and L3

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Spread Spectrum Clock Isolation

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Dual clock domain

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Quality of Service (QoS)

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Two Virtual Channels (VC) per port

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Eight Traffic Classes per port

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Weighted Round-Robin Port & VC

Arbitration

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Reliability, Availability, Serviceability

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All ports Hot-Plug capable thru I

(Hot-Plug Controller on every port)

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ECRC & Poison bit support

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Data path protection

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Memory (RAM) error correction

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Advanced Error Reporting support

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Port Status bits and GPIO available

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Per port error diagnostics

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Performance monitoring

(per port payload & header counters)

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JTAG AC/DC boundary scan

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Fatal Error (FATAL_ERR#) output signal

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INTA# output signal

Version 1.2 2009

PEX 8608

The ExpressLane

enabling users to add scalable high bandwidth non-blocking interconnection to a

wide variety of applications including communications platforms, control plane

applications and embedded systems. The PEX 8608 is well suited for fan-out,

aggregation, peer-to-peer, and intelligent I/O module applications

.

Low Packet Latency & High Performance

The PEX 8608 architecture supports packet cut-thru with a maximum latency of

130ns in x4 to x1 configuration. This, combined with large packet memory and

non-blocking internal switch architecture, provides full line rate on all ports for low-

latency applications such as communications and embedded. The low latency

enables applications to achieve high throughput and performance. In addition to low

latency, the device supports a max payload size of 2048 bytes, enabling the user to

achieve even higher throughout

.

Data Integrity

The PEX 8608 provides end-to-end CRC protection (ECRC) and Poison bit support

to enable designs that require guaranteed error-free packets. PLX also supports

data path parity and memory (RAM) error correction as packets pass through the

switch

.

Dual-Host and Fail-Over Support

The PEX 8608 supports full non-transparent bridging (NTB) functionality to allow

implementation of multi-host systems and intelligent I/O modules in applications

which require redundancy support such as communications, storage, and servers.

Non-transparent bridges allow systems to isolate host memory domains by

presenting the processor subsystem as an endpoint rather than another memory

system. Base address registers are used to translate addresses; doorbell registers are

used to send interrupts between the address domains; and scratchpad registers are

accessible from both address domains to allow inter-processor communication

.

Interoperability

The PEX 8608 is designed to be fully compliant with the PCI Express Base

Specification r2.0 and is backwards compatible to PCI Express Base Specification

r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and

polarity reversal. Furthermore, the PEX 8608 is designed for Microsoft Vista

compliance. All PLX switches undergo thorough interoperability testing in PLX’s

Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure

compatibility with PCI Express devices in the market.

Device Operation Configuration Flexibility

The PEX 8608 provides several ways to configure its operations. The device can be

configured through strapping pins, I

optional serial EEPROM. This allows for easy debug during the development phase

and functional monitoring during the operation phase

.