STC5415 datasheet(6/48 Pages) CONNOR-WINFIELD

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TM120

Rev:P1.3

Date: September 20, 2011

STC5415

Line Card Clock

Data sheet

Preliminary

STC5415 Pin Description

All I/O is LVCMOS, except for CLK1 is LVPECL/LVDS. REF4 and REF5 are LVCMOS/LVPECL/LVDS.

Table 1: Pin Description

Pin Name

Pin #

I/O

Description

AVCC

4,14

3.3V analog power input

AGND

3,15

Analog ground

VCC

8, 9, 12,

22, 32,

36, 38,

39, 45,

46, 54,

3.3V digital power input

GND

1, 7, 10,

11, 21,

31, 40,

53, 58

Digital ground

RST

Active low to reset the chip

MCLK

Master clock input (TCXO or XO)

EVENT_INTR

Event interrupt

EX_SYNC

Frame Sync signal

REF1

Reference input 1

REF2

Reference input 2

REF3

Reference input 3

REF4_P

Differential reference input 4 (LVPECL/LVDS)

REF4_N

Differential reference input 4 (LVPECL/LVDS)

REF5_P

Differential reference input 5 (LVPECL/LVDS)

REF5_N

Differential reference input 5 (LVPECL/LVDS)

CLK1_P

Clock output CLK1 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1

LVPECL or LVDS

CLK1_N

Clock output CLK1 negative, 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1

LVPECL or LVDS

CLK2

Clock output CLK2, 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G4. LVCMOS.

CLK8K

8kHz frame pulse signal, from Synthesizer F, 50% duty cycle or programmable pulse width

CLK2K

2kHz frame pulse signal, from Synthesizer F, 50% duty cycle or programmable pulse width

SRCSW

Hard-wired manual reference pre-selection

SPI bus chip select

SCLK

SPI bus clk

SDI

SPI bus data in

SDO

SPI bus data out

CLKE

SPI Clock edge selection

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