KTS6027-2 datasheet(17/41 Pages) INFINEON

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Functional Description

3 - 17

KTS6027-2, KTS6029-2

Wireless Components

Specification, July 2001

(internal amplifier, external pull-up resistor at TUNE and external RC circuitry).

The charge pump output is also switched into the high-impedance state if the

control bits T0 = 1 and T1 = 0. Here it should be noted, however, that the tuning

voltage can alter over a long period in the high-impedance state as a result of

self-discharge in the peripheral circuitry. TUNE may be switched off by the con-

trol bit OS to allow external adjustments.

If the VCO is not oscillating the PLL locks to a tuning voltage of 33 V .

By means of the control bits CP, CM, T0 and T1 the pump current can be

switched between four values by software. This programmability permits alter-

ation of the control response time of the PLL in the locked-in state. In this way

different VCO gains can be compensated, for example.

The software-switched ports PLOW, PMID, PHIGH and PFM are general-pur-

pose open-collector outputs. The test bits T0 = 0 and T1 = 1 switches the test

signals fref (i.e.fXTAL / 64) and fdiv (divided input signal) to PLOW and PMID

respectively.

The lock detector resets the lock flag FL if the width of the charge pump current

pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL

= 1, the maximum deviation of the input frequency from the programmed fre-

quency is given by

∆f = ± I

P (KVCO / fXTAL) (C1+C2) / (C1C2)

where IP is the charge pump current, KVCO the VCO gain, fXTAL the crystal oscil-

lator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-1

KTS6027-2 Evaluation Board on page 20

). As the charge pump pulses at i.e. 62.5 kHz (=

fref), it takes a maximum of 16 µs for FL to be reset after the loop has lost lock

state.

Once FL has been reset, it is set only if the charge pump pulse width is less than

250 ns for eight consecutive fref periods. Therefore it takes between 128 and

144

µs for FL to be set after the loop regains lock.

3.4.4

I2C-Bus Interface

Data is exchanged between the processor and the PLL via the I2C bus. The

clock is generated by the processor (input SCL), while pin SDA functions as an

input or output depending on the direction of the data (open collector, external

pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,

which enhance the noise immunity of the I2C bus.

The data from the processor pass through an I2C bus controller. Depending on

their function the data are subsequently stored in registers. If the bus is free,

both lines will be in the marking state (SDA, SCL are HIGH). Each telegram

begins with the start condition and ends with the stop condition. Start condition:

SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH

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