BQ76PL536APAPR datasheet(46/74 Pages) TI1

46 / 74 page

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

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7.6.15 IO_CONTROL Register (0x31)

The IO_CONTROL register controls some features of the bq76PL536A external I/O pins.

Figure 38. IO_CONTROL Register

AUX

GPIO_OUT

GPIO_IN

Reserved

SLEEP

TS2

TS1

Table 14. IO_CONTROL Register Field Descriptions

Bit

Field

Type

Reset

Description

AUX

Controls the state of the AUX output pin, which is internally

connected to REG50.

0 = Open

1 = Connected to REG50

GPIO_OUT

Controls the state of the open-drain GPIO output pin; the pin

should be programmed to 1 to use the GPIO pin as an input.

0 = Output low

1 = Open-drain

GPIO_IN

Represents the input state of GPIO pin when used as an input

0 = GPIO input is low

1 = GPIO input is high

4-3

Reserved

SLEEP

Places the device in a low-quiescent-current state. All CUV,

COV, and OT comparators are disabled. A 1-ms delay to

stabilize the reference voltage is required to exit SLEEP mode

and return to active COV, CUV monitoring.

0 = ACTIVE mode

1 = SLEEP mode

1-0

TSx

Controls the connection of the TS1:TS2 inputs to the ADC VSS

connection point. When set, the TSx(–) input is connected to

VSS. These bits should be set to 0 to reduce the current draw of

the system.

0 = Not connected

1 = Connected

7.6.16 CB_CTRL Register (0x32)

The CB_CTRL register determines the internal cell balance output state.

Figure 39. CB_CTRL Register

Reserved

CBAL[6]

CBAL[5]

CBAL[4]

CBAL[3]

CBAL[2]

CBAL[1]

Table 15. CB_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

5-0

CBAL[n]

CB_CTRL b(n = 5 to 0) (CBAL(n + 1)): This bit determines if the

CB(n) output is high or low.

0 = CB[n] output is low (default).

1 = CB[n] output is high (active).

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