BQ76PL536APAPR datasheet(48/74 Pages) TI1

48 / 74 page

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

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7.6.20 ADDRESS_CONTROL Register (0x3b)

The ADDRESS_CONTROL register allows the host to assign an address to the bq76PL536A for communication.

The default for this register is 0x00 at RESET.

Figure 43. ADDRESS_CONTROL Register

ADDR_RQST

Reserved

ADDR[5]

ADDR[4]

ADDR[3]

ADDR[2]

ADDR[1]

ADDR[0]

Table 18. ADDRESS_CONTROL Register Field Descriptions

Bit

Field

Type

Reset

Description

ADDR_RQST

This bit is written to indicate that the ADDR[0]…[5] bits have

been written to the correct address. This bit is reflected in the

DEVICE_STATUS[AR] bit.

0 = Address has not been assigned (default at RESET).

1 = Address has been assigned.

Reserved

5-0

ADDR[n]

These bits set the device address for SPI communication. This

provides to a range of addresses from 0x00 to 0x3f. Address

0x3f is reserved for broadcast messages to all connected and

addressed 76PL536 devices. The default for these 6 bits is 0x00

at RESET.

7.6.21 RESET Register (0x3c)

The RESET register allows the host to reset the bq76PL536A directly.

Writing 0xa5 causes the device to RESET. Other values are ignored.

Figure 44. RESET Register

RST[7]

RST[6]

RST[5]

RST[4]

RST[3]

RST[2]

RST[1]

RST[0]

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