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M02011

21

CMOS Transimpedance Amplifier with AGC

for Fiber Optic Networks up to 622 Mbps

Rev V5

5.0 Die Specification

Figure 5-1.

Bare Die Layout

Pad

Number

Pad

X

Y

1

AGC

–329

–76

–329

–228

3

PINK

–124

–434

4

PINA

124

–434

329

–228

6MON

329

–76

7DOUT

329

76

DOUTGND

329

228

GND

329

360

GND

255

434

GND

124

434

GND

–124

434

GND

–255

434

GND

–329

360

DOUTGND

–329

228

12

DOUT

–329

76

NOTES:

1.

GND pad. However, bonding one of each pad (if

available) on each side of the die is encouraged

for improved performance in noisy environ-

ments.

2.

Each location is an acceptable bonding location.

Notes:

Process technology: CMOS, Silicon Nitride passivation

Die thickness: 300 µm

Pad metallization: Aluminium

Die size: 880 µm x 1090

Pad opening: 86 µmsq.

Octagonal pad: 70 µm across flat PINA (70 µm x 70 µm)

Pad Centers in µm referenced to center of device

Connect backside bias to ground