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SP703EN Datasheet(PDF) 9 Page - Sipex Corporation |
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SP703EN Datasheet(HTML) 9 Page - Sipex Corporation |
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9 / 16 page  SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 9 THEORY OF OPERATION Reset Output The microprocessor's ( µP's) reset input starts the µP in a known state. When the µP is in an unknown state, it should be held in reset. The SP703/704 assert reset during power-up and prevent code execution errors during power- down or brownout conditions. On power-up, once V CC reaches 1V, RESET is guaranteed to be a logic low. As V CC rises, RESET remains low. When V CC exceeds the reset threshold, RESET will remain low for 200ms, Figure 9. If a brownout condition occurs and V CC dips below the reset threshold, RESET is triggered. Each time RESET is trig- gered, it stays low for the reset pulse width interval. If a brownout condition interrupts a previously initiated reset pulse, the reset pulse continues for another 200ms. On power-down, once V CC goes below the threshold, RESET is guaranteed to be logic low until V CC drops below 1V. RESET is also triggered by a manual reset FEATURES The SP703/704 devices provide four key func- tions: 1. A battery backup switching for CMOS RAM, CMOS microprocessors, or other logic. 2. A reset output during power-up, power-down and brownout conditions. 3. A reset pulse if the manual reset has been pulled below 0.8V for at least 150ns. 4. A 1.25V threshold detector for power-fail warning, low battery detection, or to monitor a power supply other than +5V. The SP703/704 devices differ only in their supply voltage monitor level. The SP703 generates a reset when V CC drops below 4.65V while the SP704 generates a reset below 4.4V. The SP703/704 devices are ideally suited for applications in automotive systems, intelligent instruments, and battery-powered computers and controllers. All designs into an environment where it is critical to monitor the power supply to the µP and its related digital components will find the SP703/704 ideal. Figure 8. Typical Operating Circuit GND GND RESET NMI VCC RESET PFO MR VOUT BUS VCC GND VBATT R2 R1 Unregulated Regulated +5V VCC 0.1 µF PFI DC Lithium Battery 3.6V µP CMOS RAM Pushbutton Switch |
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