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Table 8. Basic Mode Status Register (BMSR), address 0x01

Bit

Bit Name

Default

Description

100BASE-T4

0, RO/P

100BASE-T4 Capable:

0 = Device not able to perform 100BASE-T4 mode.

100BASE-TX

Full Duplex

1, RO/P

100BASE-TX Full Duplex Capable:

1 = Device able to perform 100BASE-TX in full duplex mode.

100BASE-TX

Half Duplex

1, RO/P

100BASE-TX Half Duplex Capable:

1 = Device able to perform 100BASE-TX in half duplex mode.

10BASE-T

Full Duplex

1, RO/P

10BASE-T Full Duplex Capable:

1 = Device able to perform 10BASE-T in full duplex mode.

10BASE-T

Half Duplex

1, RO/P

10BASE-T Half Duplex Capable:

1 = Device able to perform 10BASE-T in half duplex mode.

10:7

RESERVED

0, RO

RESERVED: Write as 0, read as 0.

6MF Preamble

Suppression

1, RO/P

Preamble suppression Capable:

1 = Device able to perform management transaction with preamble

suppressed, 32-bits of preamble needed only once after reset, invalid

opcode or invalid turnaround.

0 = Normal management operation.

Auto-Negotiation

Complete

0, RO

Auto-Negotiation Complete:

1 = Auto-Negotiation process complete.

0 = Auto-Negotiation process not complete.

Remote Fault

0, RO/LH

Remote Fault:

1 = Remote Fault condition detected (cleared on read or by reset).

Fault criteria: Far End Fault Indication or notification from Link Part-

ner of Remote Fault.

0 = No remote fault condition detected.

Auto-Negotiation

Ability

1, RO/P

Auto Negotiation Ability:

1 = Device is able to perform Auto-Negotiation.

0 = Device is not able to perform Auto-Negotiation.

Link Status

0, RO/LL

Link Status:

1 = Valid link established (for either 10 or 100 Mb/s operation).

0 = Link not established.

The criteria for link validity is implementation specific. The occurrence

of a link failure condition will causes the Link Status bit to clear. Once

cleared, this bit may only be set by establishing a good link condition

and a read via the management interface.

Jabber Detect

0, RO/LH

Jabber Detect: This bit only has meaning in 10 Mb/s mode.

1 = Jabber condition detected.

0 = No Jabber.

This bit is implemented with a latching function, such that the occur-

rence of a jabber condition causes it to set until it is cleared by a read

to this register by the management interface or by a reset.

Extended Capabili-

1, RO/P

Extended Capability:

1 = Extended register capabilities.

0 = Basic register set capabilities only.

DP83847 Datasheet(PDF) 31 Page - National Semiconductor (TI)

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