DP83847 datasheet(20/60 Pages) NSC

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The 100BASE-TX MLT-3 signal sourced by the TD

± com-

mon driver output pins is slew rate controlled. This should

be considered when selecting AC coupling magnetics to

ensure TP-PMD Standard compliant transition times (3 ns

< Tr < 5 ns).

The 100BASE-TX transmit TP-PMD function within the

DP83847 is capable of sourcing only MLT-3 encoded data.

Binary output from the TD

± outputs is not possible in 100

Mb/s mode.

3.3 100BASE-TX RECEIVER

The 100BASE-TX receiver consists of several functional

blocks which convert the scrambled MLT-3 125 Mb/s serial

data stream to synchronous 4-bit nibble data that is pro-

vided to the MII. Because the 100BASE-TX TP-PMD is

integrated, the differential input pins, RD

±, can be directly

routed from the AC coupling magnetics.

See Figure 7 for a block diagram of the 100BASE-TX

receive function. This provides an overview of each func-

tional block within the 100BASE-TX receive section.

The Receive section consists of the following functional

blocks:

—ADC

— Input and BLW Compensation

— Signal Detect

— Digital Adaptive Equalization

— MLT-3 to Binary Decoder

— Clock Recovery Module

— NRZI to NRZ Decoder

— Serial to Parallel

— DESCRAMBLER (bypass option)

— Code Group Alignment

— 4B/5B Decoder (bypass option)

— Link Integrity Monitor

— Bad SSD Detection

The bypass option for the functional blocks within the

100BASE-TX receiver provides flexibility for applications

where data conversion is not always required.

3.3.1 Input and Base Line Wander Compensation

Unlike the DP83223V Twister, the DP83847 requires no

external attenuation circuitry at its receive inputs, RD

±. It

accepts TP-PMD compliant waveforms directly, requiring

only a 100

Ω termination plus a simple 1:1 transformer.

The DP83847 is completely ANSI TP-PMD compliant and

includes Base Line Wander (BLW) compensation. The

BLW compensation block can successfully recover the TP-

PMD defined “killer” pattern and pass it to the digital adap-

tive equalization block.

BLW can generally be defined as the change in the aver-

age DC content, over time, of an AC coupled digital trans-

mission over a given transmission medium. (i.e., copper

wire).

BLW results from the interaction between the low fre-

quency components of a transmitted bit stream and the fre-

quency response of the AC coupling component(s) within

the transmission system. If the low frequency content of

the digital bit stream goes below the low frequency pole of

the AC coupling transformers then the droop characteris-

tics of the transformers will dominate resulting in potentially

serious BLW.

The digital oscilloscope plot provided in Figure 6 illustrates

the severity of the BLW event that can theoretically be gen-

erated during 100BASE-TX packet transmission. This

event consists of approximately 800 mV of DC offset for a

Figure 6. 100BASE-TX BLW Event

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