DP83850CVF datasheet(13/37 Pages) NSC

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3.0 Functional Description (Continued)

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Subsequently writing 0000h to the PAGE register in Regis-

ter Page 1 switches the registers back to Register Page 0.

All accesses to DP83850C registers and counters, and to

the connected Physical Layer devices (via the DP83850C),

are performed serially using the RDIO and RDC pins. The

RDC clock is limited to a frequency no greater than

2.5MHz. This interface implements the serial management

protocol deﬁned by the MII speciﬁcation, IEEE 802.3u

clause 22. The protocol uses bit streams with the following

format:

For Read operation: <start><opcode><device addr><reg

addr> [turnaround] 0<data>.

For Write operation: <start><opcode><device addr><reg

addr> <10><data>.

This protocol allows for up to 32 devices (DP83850Cs or

other MII compliant devices) to be connected, each with a

unique address and up to 32 16-bit registers. Devices are

cascaded on the RDIO and RDC signals.

Since the RDIO pin is shared for both read and write oper-

ations, it must only be driven at the proper time. The serial

protocol assumes that there is only one master (generally,

the management entity's processor) and one or more slave

devices (generally, the Physical Layer or DP83850C chips).

The master drives RDIO at all times except when, during a

slave read operation, the addressed slave places the seri-

alized read data onto the RDIO line after the line turn-

around ﬁeld's ﬁrst bit.

For unmanaged systems that do not use the DP83856

100RIB device for repeater management, it is important to

provide the 100RIC with a minimum of 3 cycles of RDC

during device reset. If the minimum number of cycles of

RDC is not provided, the Serial Register Access Logic

block may not be properly reset and as a result RDIO may

not function properly. The 100RIB provides continuous

RDC cycles, and eliminates this concern.

The ﬁelds of the protocol are deﬁned in Table 3-1. In order

for the protocol to work, all serial logic must ﬁrst be “syn-

chronized” to incoming data. A preamble of 32 consecutive

1's transmitted before the <start> ﬁeld ensures "data lock".

DP83850CVF Datasheet(PDF) 13 Page - National Semiconductor (TI)