AD9860 datasheet(7/32 Pages) AD

7 / 32 page

REV. 0

AD9860/AD9862

–7–

Pin No.

Mnemonic

Function

Clock Pins

DLL_Lock

DLL Lock Indicator Pin

11, 16

AGND

DLL Analog Ground Pins

No Connect

AVDD

DLL Analog Supply Pin

OSC1

Single Ended Input Clock

(or Crystal Oscillator Input)

OSC2

Crystal Oscillator Input

CLKSEL

Controls CLKOUT1 Rate

CLKOUT2

Clock Output Generated from Input

Clock (DLL Multiplier Setting

and CLKOUT2 Divide Factor)

CLKOUT1

Clock Output Generated from

Input Clock (1

if CLKSEL = 1

or /2 if CLKSEL = 0)

Various Pins

AUX_ADC_A1

Auxiliary ADC A Input 1

3, 4, 13

AVDD

Analog Power Pins

2, 9

AGND

Analog Ground Pins

SIGDELT

Digital Output from

Programmable Sigma-Delta

AUX_DAC_A

Auxiliary DAC A Output

AUX_DAC_B

Auxiliary DAC B Output

AUX_DAC_C

Auxiliary DAC C Output

33, 36, 53, DVDD

Digital Power Supply Pin

59, 61, 66,

34, 35, 52, DGND

Digital Ground Pin

58, 60, 67,

SCLK

Serial Bus Clock Input

SDO

Serial Bus Data Bit

SDIO

Serial Bus Data Bit

SEN

Serial Bus Enable

RESETB

Reset (SPI Registers and Logic)

AUX_SPI_do

Optional Auxiliary ADC Serial Bus

Data Out Bit

AUX_SPI_clk

Optional Auxiliary ADC Serial Bus

Data Out Latch Clock

AUX_SPI_csb

Optional Auxiliary ADC Serial Bus

Chip Select Bit

128

AUX_ADC_A2

Auxiliary ADC A Input 2

126

AUX_ADC_B1

Auxiliary ADC B Input 1

125

AUX_ADC_B2

Auxiliary ADC B Input 2

127

AUX_ADC_REF Auxiliary ADC Reference

Pin No.

Mnemonic

Function

Receive Pins

68/70–79

D0A to

10-/12-Bit ADC Output of

D9A/D11A

Receive Channel A

80/82–91

D0B to

10-/12-Bit ADC Output of

D9B/D11B

Receive Channel B

RxSYNC

Synchronization Clock for

Channel A and Channel B Rx Paths

98, 99,

AVDD

Analog Supply Pins

104, 105,

117, 118,

123, 124,

100, 103, AGND

Analog Ground Pins

106, 109,

110, 112,

113, 116,

119, 122,

101

REFT_B

Top Reference Decoupling for

Channel B ADC

102

REFB_B

Bottom Reference Decoupling

for Channel B ADC

107

VIN+B

Receive Channel B Differential (+) Input

108

VIN–B

Receive Channel B Differential ( ) Input

111

VREF

Internal ADC Voltage Reference

114

VIN–A

Receive Channel A Differential ( ) Input

115

VIN+A

Receive Channel A Differential (+) Input

120

REFB_A

Bottom Reference Decoupling for

Channel A ADC

121

REFT_A

Top Reference Decoupling for

Channel A ADC

Transmit Pins

18, 20

AVDD

Analog Supply Pins

23, 32

19, 24,

AGND

Analog Ground Pins

27, 28, 31

REFIO

Reference Output, 1.2 V Nominal

FSADJ

Full-Scale Current Adjust

IOUT–ATransmit Channel A DAC

Differential ( ) Output

IOUT+A

Transmit Channel A DAC

Differential (+) Output

IOUT+B

Transmit Channel B DAC

Differential (+) Output

IOUT–BTransmit Channel B DAC

Differential ( ) Output

37–48/50 Tx11/Tx13

12-/14-Bit Transmit DAC Data

to Tx0

(Interleaved Data when Required)

TxSYNC

Synchronization Input for Transmitter

MODE/

Configures Default Timing Mode,

TxBLANK

* Controls Tx Digital Power Down

*The logic level of the Mode/TxBLANK pin at power up defines the default timing

mode; a logic low configures Normal Operation, logic high configures Alternate

Operation Mode.

PIN FUNCTION DESCRIPTIONS

AD9860 Datasheet(PDF) 7 Page - Analog Devices

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