REV. 0

–18–

AD9860/AD9862

Read Operation

The read back of registers is a single data byte operation. The

readback can be configured to use three pins or four pins and can

be formatted as MSB first or LSB first. The instruction header

is written to the device either MSB or LSB first (depending on

the mode) followed by the 8-bit output data (appropriately MSB

or LSB justified). By default, the output data is sent to the dedicated

output pin (SDO). 3-wire operation can be configured by set-

ting the SDIO BiDir register. In 3-wire mode, the SDIO pin

will become an output pin after receiving the 8-bit instruction

header with a read back request.

Figure 2a shows an MSB first, 4-pin SPI read; Figure 2b shows an

MSB first, 3-pin read; and Figure 2c shows an LSB first, 4-pin read.

SYSTEM BLOCK DESCRIPTION

The AD9860/AD9862 integrates transmit and receive paths with

digital signal processing blocks and auxiliary features. The auxiliary

SDIO

SEN

SCLK

INSTRUCTION HEADER (REGISTER N)

SDO

SDIO

SEN

SCLK

SDIO

SEN

SCLK

SDO

DON’T CARE

DON’T CARE

DON’T CARE

DON’T CARE

DON’T CARE

DON’T CARE

R/nW

2/n1

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

OUTPUT REGISTER DATA

DON’T CARE

DON’T CARE

R/nW

2/n1

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

DON’T CARE

DON’T CARE

OUTPUT REGISTER DATA

INSTRUCTION HEADER

DON’T CARE

R/nW

2/n1

DON’T CARE

DON’T CARE

DON’T CARE

DON’T CARE

DON’T CARE

A0

A1

A2

A3

A4

A5

D0

D1

D2

D3

D4

D5

D6

D7

OUTPUT REGISTER DATA

INSTRUCTION HEADER

Figure 2. SPI Read Examples a. (top) 4-Wire Interface, MSB first; b. (middle) 3-Wire Interface, MSB first;

c. (bottom) 4-Wire Interface, LSB first

features include two auxiliary ADCs, a programmable sigma-delta

output, three auxiliary DACs, integrated clock circuitry to generate

all internal clocks, and buffered output clocks from a single input

reference.

The AD9860/AD9862 system functionality is described in the

following four sections: the Transmit Block, Receive Block, Timing

Generation Block, and the Auxiliary Function Block. The following

sections provide a brief description of the blocks and applications

for the four sections.

TRANSMIT SECTION COMPONENTS

The transmit block (Tx) accepts and can process real or complex

data. The Tx interface is configurable for a variety of data formats

and has special processing options such as interpolation and Hilbert

filters. A detailed block diagram of the AD9860/AD9862 transmit

path is shown in Figure 3. The transmit block diagram is broken

into these stages: DAC (Block A), Coarse Modulation (Block B),