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CY7C68310 Datasheet(PDF) 15 Page - Cypress Semiconductor

Part # CY7C68310
Description  ISD-300LP??Low-Power USB 2.0 to ATA/ATAPI Bridge IC
PDF  34 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C68310 Datasheet(HTML) 15 Page - Cypress Semiconductor

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CY7C68310
Document 38-08030 Rev. *H
Page 15 of 34
‘1’ = USB FS only – do not allow HS negotiation during USB
reset
VS/MSC SOFT_RESET
Bit(1)
Vendor-specific/MSC SOFT_RESET control.
‘0’ = Vendor-specific USB command utilized for
SOFT_RESET
‘1’ = Mass Storage Class USB command utilized for
SOFT_RESET
DISKRDY Polarity
Bit (0)
DISKRDY active polarity. DISKRDY Polarity is ignored if
IMODE is set to ‘1’. During IMODE operation DISKRDY
polarity is active HIGH.
‘0’ = Active HIGH polarity
‘1’ = Active LOW polarity
0x06
ATA Command Designator
Value in CBW CB field that designates if the CB is decoded
as vendor-specific ATA/CFG commands instead of the
ATAPI command block.
0x24
0x07
Reserved
Bits (7:1)– must be set to ‘0’.
0x01
Retry ATAPI
Bit (0)
This bit enables the CY7C68310 to accommodate ATAPI
devices that take longer to initialize than what is allowed in
the ATA/ATAPI-6 specification.
‘1’ = Retry ATAPI commands
‘0’ = Normal ATAPI timing
0x08
Initialization Status
Bit (7) – Read only
0x00
Drive Initialization Status.
If set, indicates the drive initialization sequence state
machine is active.
Force ATA Device
Bit (6)
Allows software to manually enable ATA Translation with
devices that do not support CY7C68310 device initialization
algorithms. Force ATA Device must be set to ‘1’ in
conjunction with Skip ATA/ATAPI Device Initialization and
ATA Translation Enable.
Skip ATA/ATAPI Device Initial-
ization
Bit (5)
Forces the CY7C68310 to skip device initialization upon
startup. This bit should be cleared for IMODE operation. The
USB device driver must initialize the attached device (if
required) when this bit is set. For ATAPI devices, the host
driver must issue an IDENTIFY command utilizing ATA.
‘0’ = normal operation
‘1’ = only reset the device and write the device control
register prior to processing commands
Reserved
Bits (4:3) – must be set to ‘0’.
Last LUN Identifier
Bits (2:0)
Maximum number of LUNs device supports.
0x09
ATAEN
Bit (7) – Read only.
0x01
Holds the current logic state of the ATAEN pin.
Table 6-2. EEPROM Organization (continued)
I2C
Address
Field Name
Field Description
Required
I2C Data
Example
I2C Data



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