CY7C68310
Document 38-08030 Rev. *H
Page 32 of 34
14.0
Package Diagram
15.0
PCB Layout Recommendations
The CY7C68310 contains high-speed analog circuitry that is
sensitive to system noise. In particular, noise on both analog
and digital power supplies must be minimized to ensure
reliable, high-performance operation. Special attention should
also be given to the design of the frequency generation,
voltage reference, and USB interface circuits. Cypress recom-
mends using the following guidelines in designing any product
that uses the CY7C68310.
• The 3.3V power rail must remain above the 2.5V rail at all
times for proper device operation.
• DP and DM trace lengths should be kept to within 2 mm of
each other and must not exceed 37 mm in total length, with
a preferred length of 20–30 mm.
• Maintain a solid ground plane under the DP and DM traces.
Do not allow the plane to be split under these traces.
• Do not place vias on the DP or DM traces.
• Isolate the DP and DM traces from all other signal traces
by no less than 10 mm.
• The DP and DM common mode trace impedance should be
controlled to 45
Ω with total differential impedance controlled
to 90
Ω (±10%).
• The VDD power plane should be as solid as possible with
direct paths from the voltage regulator to all discrete com-
ponents. A four layer board is required with inner layers
dedicated to power and ground planes. Digital ground
should cover one entire layer of the design.
• Analog and digital power planes must be isolated using in-
ductors.
• Ceramic or tantalum capacitors are required. Do not use
electrolytic capacitors. Electrolytic capacitors have higher
lead inductance and series resistance values that have
been observed to contribute to increased power supply
noise.
• Adequate bypass capacitance must be implemented very
near to the CY7C68310 power pins. One ceramic bypass
capacitor per power/ground pair is recommended.
• All termination and pull-up resistors (including DP and DM) should be placed within 5 mm of the CY7C68310 pins.
• The crystal and RREF external resistor components should be placed as near the CY7C68310 pins as possible.
Figure 14-1. 80-pin TQFP Package Diagram
80-lead Thin Plastic Quad Flat Pack (12 x 12 x 1.0 mm) A8012x12
51-85175-**
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