TMS570LS0332PZ datasheet(32/110 Pages) TI1

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CPU 1

CPU 2

2cycledelay

CCM-R4

compare

CPU1CLK

CPU2CLK

compare

error

Input+Control

Output+Control

TMS570LS0432, TMS570LS0332

SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

www.ti.com

6.4.4

Duplicate clock tree after GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU

running at the same frequency and in phase to the clock of CPU1. See Figure 6-3.

6.4.5

ARM Cortex-R4 CPU Compare Module (CCM) for Safety

This device has two ARM Cortex-R4 CPU cores, where the output signals of both CPUs are compared in

the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in

a different way as shown in Figure 6-3.

Figure 6-3. Dual Core Implementation

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of

both CPUs before the registers are used, including function calls where the register values are pushed

onto the stack.

6.4.6

CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4 CPU Cores using the Deterministic

Logic BIST Controller as the test engine.

The main features of the self-test controller are:

•

Ability to divide the complete test run into independent test intervals

•

Capable of running the complete test or running a few intervals at a time

•

Ability to continue from the last executed interval (test set) or to restart from the beginning (first test

set)

•

Complete isolation of the self-tested CPU core from the rest of the system during the self-test run

•

Ability to capture the failure interval number

•

Timeout counter for the CPU self-test run as a fail-safe feature

System Information and Electrical Specifications

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TMS570LS0332PZ Datasheet(PDF) 32 Page - Texas Instruments

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