VSP1221 datasheet(6/26 Pages) TI

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TIMING REQUIREMENTS

SAMPLE AND CONVERSION TIMING

N+1

N−10

tWSHD

tCCD_SHP

SHP

SHD

ADCCLK

tCCD_SHD

tDSHD

tADCCLK

tADC_SHD

tWADC

tHOLD

tOD

D0–D11

N−9

N−8

N−7

tWADC

DIN

(CCD IN)

tWSHP

tDSHP

VSP1221

SLES012A – SEPTEMBER 2001 – REVISED JULY 2004

Figure 2. Sample and Conversion Timing

SAMPLE AND CONVERSION TIMING

PARAMETERS

MIN

TYP

MAX

UNIT

tADCCLK

ADC clock period

tWADC

ADC high or low width

tWSHP

SHP pulse width

tWSHD

SHD pulse width

tCCD_SHP

CCD reset start to SHP rising edge

See Note(1)

tCCD_SHD

CCD data start to SHD rising edge

See Note(2)

tADC_SHD

ADC falling edge to SHD rising edge

tDSHP

Sampling delay, reset

1.75

tDSHD

Sampling delay, data

tHOLD

Output hold time

tOD

Output delay

(1)

Best performance if tCCD_SHP > 15 ns

Good performance if 10 ns < tCCD_SHP < 15 ns

Poor performance if tCCD_SHP < 10 ns

(2)

Best performance if tCCD_SHD > 19 ns

Good performance if 10 ns < tCCD_SHD < 19 ns

Poor performance if tCCD_SHD < 15 ns

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