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12

+

−

2x8

8

D0/SDO

10

DIN

PIN

CLAMP

CLPDM

CLREF

TP1

TP2

AVDD

INT. REF.

REFP ISET REFM

DVDD

DIVDD

12-Bit

ADC

Digital

PGA

Analog

PGA

Offset

Correction

8-Bit

DAC

DACO1

CFG1

CFG2

DAC

Register

8-Bit

DAC

DACO2

DAC

Register

AVSS

VSS

PGA

Register

Vb

Register

OB DAC

OB

Calibration

Circuit

Serial

Port

DVSS

DIVSS

Logic

Control

3-State

Latch

OE

D11

RESET

ADCCLK

SHD

SHP

BLKG

CLPOB

STBY

SLOAD

SCLK

SDIN

SCKP

CDS

ABSOLUTE MAXIMUM RATINGS

(1)

VSP1221

SLES012A – SEPTEMBER 2001 – REVISED JULY 2004

Terminal Functions (continued)

TERMINAL

DESCRIPTION

NAME

PIN

SCKP

45

DI

SCKP - Serial clock polarity:

High = Sample serial data on rising edge of serial clock (pin 48)

Low = Sample serial data on falling edge of serial clock (pin 48)

SLOAD

46

DI

Serial data latch

SDIN

47

DI

Serial data input

SCLK

48

DI

Serial clock input

FUNCTIONAL BLOCK DIAGRAM

Figure 1. Internal Block Diagram fo the VSP1221

over operating free-air temperature range (unless otherwise noted)

UNIT

-0.3 V to 6.5 V

Analog input voltage

-0.3 V to AVDD + 0.3 V

Digital input voltage

-0.3 V to DVDD + 0.3 V

0

°C to 150°C

-65

°C to 150°C

Lead temperature, (10 sec)

260

°C

(1)

Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under ,,recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

3