M38B53M4-059FP datasheet(26/69 Pages) MITSUBISHI

26 / 69 page

MITSUBISHI MICROCOMPUTERS

38B5 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

(1) Serial I/O1 Operation

Either the internal synchronous clock or external synchronous clock

can be selected by the serial I/O1 synchronous clock selection bits

(b2 and b3 of address 001916) of serial I/O1 control register 1 as

synchronous clock for serial transfer.

The internal synchronous clock has a built-in dedicated divider where

7 different clocks are selected by the internal synchronous clock

selection bits (b5, b6 and b7 of address 001C16) of serial I/O1

control register 3.

________

The P62/SRDY1/AN8, P64/INT4/SBUSY1/AN10, and P65/SSTB1/AN11

pins each select either I/O port or handshake I/O signal by the

serial I/O1 synchronous clock selection bits (b2 and b3 of address

________

001916) of serial I/O1 control register 1 as well as the P62/SRDY1 •

P64/SBUSY1 pin control bits (b0 to b3 of address 001A16) of serial

I/O1 control register 2.

For the SOUT1 being used as an output pin, either CMOS output or

N-channel open-drain output is selected by the P51/SOUT1 P-chan-

nel output disable bit (b7 of address 001A16) of serial I/O1 control

Either output active or high-impedance can be selected as a SOUT1

pin state at serial non-transfer by the SOUT1 pin control bit (b6 of

address 001A16) of serial I/O1 control register 2. However, when

the external synchronous clock is selected, perform the following

setup to put the SOUT1 pin into a high-impedance state.

When the SCLK1 input is “H” after completion of transfer, set the

SOUT1 pin control bit to “1.”

When the SCLK1 input goes to “L” after the start of the next serial

transfer, the SOUT1 pin control bit is automatically reset to “0” and

put into an output active state.

Regardless of whether the internal synchronous clock or external

synchronous clock is selected, the full duplex mode and the trans-

mit-only mode are available for serial transfer, one of which is se-

lected by the transfer mode selection bit (b5 of address 001916) of

serial I/O1 control register 1.

Either LSB first or MSB first is selected for the I/O sequence of the

serial transfer bit strings by the transfer direction selection bit (b6 of

address 001916) of serial I/O1 control register 1.

When using serial I/O1, first select either 8-bit serial I/O or auto-

matic transfer serial I/O by the serial transfer selection bits (b0 and

b1 of address 001916) of serial I/O1 control register 1, after comple-

tion of the above bit setup. Next, set the serial I/O initialization bit

(b4 of address 001916) of serial I/O1 control register 1 to “1” (Serial

I/O enable) .

When stopping serial transfer while data is being transferred, re-

gardless of whether the internal or external synchronous clock is

selected, reset the serial I/O initialization bit (b4) to “0.”

Serial I/O1 control register 3

(SIO1CON3 (SC13): address 001C16)

Internal synchronous clock selection bits

000:f(XIN)/4 or f(XCIN)/8

001:f(XIN)/8 or f(XCIN)/16

010:f(XIN)/16 or f(XCIN)/32

011:f(XIN)/32 or f(XCIN)/64

100:f(XIN)/64 or f(XCIN)/128

101:f(XIN)/128 or f(XCIN)/256

110:f(XIN)/256 or f(XCIN)/512

Automatic transfer interval set bits

00000:2cycles of transfer clocks

00001:3cycles of transfer clocks

11110:32cycles of transfer clocks

11111:33cycles of transfer clocks

Data is written to a latch and read from a decrement counter.

Fig. 21 Structure of Serial I/O1 Control Register 3

M38B53M4-059FP Datasheet(PDF) 26 Page - Mitsubishi Electric Semiconductor

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