DA7211 datasheet(3/105 Pages) DIALOG

3 / 105 page

DA7211

Ultra-low power stereo codec

Company confidential

Datasheet

Revision 3e

15-Oct-2015

CFR0011-120-00 Rev 5

3 of 105

9.1

Digital audio interface (DAI) ................................................................................................ 49

9.1.1

Operation modes DAI interface ........................................................................... 49

9.1.2

Right justified mode ............................................................................................. 49

9.1.3

Left justified mode................................................................................................ 50

9.1.4

I2S mode ............................................................................................................. 50

9.1.5

DSP mode ........................................................................................................... 50

9.1.6

TDM mode ........................................................................................................... 50

9.1.7

Clocking schemes................................................................................................ 51

9.1.8

Master mode ........................................................................................................ 53

9.1.9

Programming master and 32 kHz mode

– PLL enabled ..................................... 55

9.2

Slave mode ......................................................................................................................... 57

9.2.1

Conditions: ........................................................................................................... 57

9.2.2

Programming slave mode

– PLL not enabled ..................................................... 57

9.2.3

Programming slave mode

– PLL enabled ........................................................... 59

9.2.4

32 kHz master or slave mode .............................................................................. 61

9.2.5

Phase locked loop (PLL)...................................................................................... 61

9.2.6

Control interface .................................................................................................. 62

9.2.7

2-wire communication.......................................................................................... 62

9.2.8

Details of the 2-wire control bus protocol ............................................................ 63

10 Register definitions ..................................................................................................................... 65

10.1 Register map....................................................................................................................... 65

10.2 Control and status registers ................................................................................................ 68

10.3 Codec registers .................................................................................................................. 70

10.4 GP filter engine ................................................................................................................... 89

10.5 ALC level controls ............................................................................................................... 99

11 Package information ................................................................................................................. 102

11.1 Package outlines ............................................................................................................... 102

11.2 Soldering information ........................................................................................................ 102

12 Ordering information ................................................................................................................ 102

13 Applications information .......................................................................................................... 103

13.1 Supporting information ...................................................................................................... 103

13.2 Minimum component recommendations ........................................................................... 103

13.3 General component suggestions ...................................................................................... 104

Figures

Figure 1: DA7211 block diagram ........................................................................................................... 9

Figure 2: DA7211 pad arrangement (bottom view ball side up).......................................................... 10

Figure 3: DA7211 power supply topology ........................................................................................... 12

Figure 4: I2S/DSP timing diagram ....................................................................................................... 23

Figure 5: 2-wire control timing diagram ............................................................................................... 24

Figure 6: Typical microphone applications .......................................................................................... 27

Figure 7: ADC and DAC DC blocking (cut-

off frequency setting ‘00’ to ‘11’, 16 kHz) ......................... 29

Figure 8: ADC pass band attenuation (audio mode, 48 kHz).............................................................. 29

Figure 9: ADC pass band suppression (audio mode, 48 kHz) ............................................................ 30

Figure 10: Operation of ALC................................................................................................................ 30

Figure 11: DAC DC blocking (cut-

off frequency setting ‘00’ to ‘11’, 48 kHz)....................................... 33

Figure 12: DAC pass band attenuation (audio mode, 48 kHz)............................................................ 34

DA7211 Datasheet(PDF) 3 Page - Dialog Semiconductor

DA7211 Datasheet(HTML) 3 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL