ST92185B datasheet(66/178 Pages) STMICROELECTRONICS

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ST92185B - TIMING AND CLOCK CONTROLLER

PLL CLOCK CONTROL REGISTER (PXCCR)

R251 - Read/Write

Reset value: 0000 0000 (00h)

Bit 7= PXCE.

Pixel Clock Enable bit.

0: Pixel and TDSRAM interface clocks are blocked

1: Pixel clock is sent to the display controller and

TDSRAM interface.

Bit 6:0= These bits are reserved.

SLICER

CLOCK

CONTROL

(SLCCR)

R252 - Read/ Write

Reset value: 0000 0000 (00h)

The HALT mode forces the register to its initializa-

tion state.

Bit 7:5 = These bits are reserved.

Bit 4= VMOD:

Video mode selection.

This bit is used to select either 50Hz or 60Hz video

mode. It is set and cleared by software.

0: 50 Hz.

1: 60 Hz.

Bit 3:0= These bits are reserved.

5.2.1 Register Mapping

The Timing Controller has 4 dedicated registers,

mapped in a ST9+ register file page (the page ad-

dress is 39 (27h)), as follows :

210

PXCE

VMOD

Page 39 (27h)

FEh

Skew Corrector Control Register

SKCCR

FDh

Main Clock Control Register

MCCR

FCh

SLicer Clock Control Register

SLCCR

FBh

Pixel Clock Control Register

PXCCR

ST92185B Datasheet(PDF) 66 Page - STMicroelectronics

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