ST92185B datasheet(57/178 Pages) STMICROELECTRONICS

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ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU)

4 RESET AND CLOCK CONTROL UNIT (RCCU)

4.1 INTRODUCTION

The Reset Control Unit comprises two distinct sec-

tions:

– An oscillator that uses an external quartz crystal.

– The Reset/Stop Manager, which detects and

flags Hardware, Software and Watchdog gener-

ated resets.

4.2 RESET / STOP MANAGER

The RESET/STOP Manager resets the device

when one of the three following triggering events

occurs:

– A hardware reset, consequence of a low level on

the RESET pin.

– A software reset, consequence of an HALT in-

struction when enabled.

– A Watchdog end of count.

The RESET input is schmitt triggered.

Note: The memorized Internal Reset (called RE-

SETO) will be maintained active for a duration of

32768 Oscin periods (about 8 ms for a 4 MHz crys-

tal) after the external input is released (set high).

This RESETO internal Reset signal is output on

the I/O port bit P3.7 (active low) during the whole

reset phase until the P3.7 configuration is changed

by software. The true internal reset (to all macro-

cells) will only be released 511 Reference clock

periods after the Memorized Internal reset is re-

leased.

It is possible to know which was the last RESET

triggering event, by reading bits 5 and 6 of register

SDRATH.

Figure 29. Reset Overview

Build-up Counter

RCCU

True

RESET

RESETO

Memorized

Reset

Internal

Reset

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