DS2155 datasheet(3/262 Pages) DALLAS

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DS2156

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8.2

T1 TRANSMIT TRANSPARENCY .....................................................................................................................57

8.3

AIS-CI AND RAI-CI GENERATION AND DETECTION ....................................................................................57

8.4

T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION.......................................................................58

TABLE 8-A. T1 ALARM CRITERIA ..........................................................................................................................60

E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..............................................61

9.1

E1 CONTROL REGISTERS ...............................................................................................................................61

TABLE 9-A. E1 SYNC/RESYNC CRITERIA ...............................................................................................................62

9.2

AUTOMATIC ALARM GENERATION................................................................................................................65

9.3

E1 INFORMATION REGISTERS........................................................................................................................66

TABLE 9-B. E1 ALARM CRITERIA...........................................................................................................................67

10.

COMMON CONTROL AND STATUS REGISTERS ............................................................................68

10.1

T1/E1 STATUS REGISTERS ........................................................................................................................69

11.

I/O PIN CONFIGURATION OPTIONS...................................................................................................75

12.

LOOPBACK CONFIGURATION ............................................................................................................77

12.1

PER-CHANNEL LOOPBACK ........................................................................................................................79

13.

ERROR COUNT REGISTERS .................................................................................................................81

13.1

LINE-CODE VIOLATION COUNT REGISTER (LCVCR)...............................................................................82

13.1.1

T1 Operation.........................................................................................................................................82

TABLE 13-A. T1 LINE-CODE VIOLATION COUNTING OPTIONS..............................................................................82

13.1.2

E1 Operation.........................................................................................................................................82

TABLE 13-B. E1 LINE-CODE VIOLATION COUNTING OPTIONS ..............................................................................82

13.2

PATH CODE VIOLATION COUNT REGISTER (PCVCR) ..............................................................................84

13.2.1

T1 Operation.........................................................................................................................................84

TABLE 13-C. T1 PATH CODE VIOLATION COUNTING ARRANGEMENTS ................................................................84

13.2.2

E1 Operation.........................................................................................................................................84

13.3

FRAMES OUT-OF-SYNC COUNT REGISTER (FOSCR)................................................................................85

13.3.1

T1 Operation.........................................................................................................................................85

TABLE 13-D. T1 FRAMES OUT-OF-SYNC COUNTING ARRANGEMENTS .................................................................85

13.3.2

E1 Operation.........................................................................................................................................85

13.4

E-BIT COUNTER (EBCR)...........................................................................................................................86

14.

DS0 MONITORING FUNCTION .............................................................................................................87

15.

SIGNALING OPERATION .......................................................................................................................89

15.1

RECEIVE SIGNALING .................................................................................................................................89

FIGURE 15-1. SIMPLIFIED DIAGRAM OF RECEIVE SIGNALING PATH ......................................................................89

15.1.1

Processor-Based Signaling...................................................................................................................89

15.1.2

Hardware-Based Receive Signaling .....................................................................................................90

15.2

TRANSMIT SIGNALING...............................................................................................................................95

FIGURE 15-2. SIMPLIFIED DIAGRAM OF TRANSMIT SIGNALING PATH ...................................................................95

15.2.1

Processor-Based Mode .........................................................................................................................95

TABLE 15-A. TIME SLOT NUMBERING SCHEMES ...................................................................................................96

15.2.2

Software Signaling Insertion-Enable Registers, E1 CAS Mode............................................................99

15.2.3

Software Signaling Insertion-Enable Registers, T1 Mode..................................................................101

15.2.4

Hardware-Based Mode.......................................................................................................................101

16.

PER-CHANNEL IDLE CODE GENERATION ....................................................................................102

TABLE 16-A. IDLE-CODE ARRAY ADDRESS MAPPING .........................................................................................102

16.1

IDLE-CODE PROGRAMMING EXAMPLES..................................................................................................103

TABLE 16-B. GRIC AND GTIC FUNCTIONS .........................................................................................................104

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