MB3773 datasheet(7/31 Pages) CYPRESS

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MB3773

Document Number: 002-08513 Rev. *A

Page 7 of 31

4. Operation Sequence

1. When Vcc rises to about 0.8 V, RESET goes “Low” and RESET goes “High”.

The pull-up current of approximately 1 μA (Vcc = 0.8 V) is output from RESET.

2. When Vcc rises to VSH ( := 4.3V) , the charge with CT starts.

At this time, the output is being reset.

3. When CT begins charging, RESET goes “High” and RESET goes “Low”.

After TPR reset of the output is released.

Reset hold time: TPR (ms) := 1000 × CT (μF)

After releasing reset, the discharge of CT starts, and watch-dog timer operation starts.

TPR is not influenced by the CK input.

4. C changes from the discharge into the charge if the clock (Negative edge) is input to the CK terminal while discharging CT.

5. C changes from the charge into the discharge when the voltage of CT reaches a constant

threshold ( := 1.4 V) .

4 and 5 are repeated while a normal clock is input by the logic system.

6. When the clock is cut off, gets, and the voltage of CT falls on threshold ( := 0.4 V) of reset on, RESET goes “Low” and RESET goes

“High”.

Discharge time of CT until reset is output: TWD is watch-dog timer monitoring time.

TWD (ms) := 100 × CT (μF)

Because the charging time of CT is added at accurate time from stop of the clock and getting to the output of reset of the clock,

TWD becomes maximum TWD  TWR by minimum TWD.

7. Reset time in operating watch-dog timer: TWR is charging time where the voltage of CT goes up to off

threshold ( := 1.4 V) for reset.

TWR (ms) := 20 × CT (μF)

Reset of the output is released after CT reaches an off threshold for reset, and CT starts the discharge, after that if the clock is

normally input, operation repeats 4 and 5, when the clock is cut off, operationrepeats 6 and 7.

8. When Vcc falls on VSL ( := 4.2 V) , reset is output. CT is rapidly discharged of at the same time.

9. When Vcc goes up to VSH, the charge with CT is started.

When Vcc is momentarily low,

After falling VSL or less Vcc, the time to going up is the standard value of the Vcc input pulse width in VSH or more.

After the charge of CT is discharged, the charge is started if it is TPI or more.

10.Reset of the output is released after TPR, after Vcc becomes VSH or more, and the watch-dog timer starts. After that, when Vcc

becomes VSL or less, 8 to 10 is repeated.

11.While power supply is off, when Vcc becomes VSL or less, reset is output.

12.The reset output is maintained until Vcc becomes 0.8 V when Vcc falls on 0 V.

MB3773 Datasheet(PDF) 7 Page - Cypress Semiconductor