HT48R10A datasheet(12/42 Pages) HOLTEK

12 / 42 page

HT48R10A-1

Rev. 1.20

July 2, 2001

The HALT mode stops the system oscillator

and ignores an external signal to conserve

power.

If an RC oscillator is used, an external resistor

between OSC1 and VDD is required and the

resistance must range from 51kW to 1MW. The

system clock, divided by 4, is available on

OSC2, which can be used to synchronize exter-

nal logic. The RC oscillator provides the most

cost effective solution. However, the frequency

of oscillation may vary with VDD, tempera-

tures and the chip itself due to process varia-

tions. It is, therefore, not suitable for timing

sensitive operations where an accurate oscilla-

tor frequency is desired.

If the Crystal oscillator is used, a crystal across

OSC1 and OSC2 is needed to provide the feed-

back and phase shift required for the oscillator,

and no other external components are required.

Instead of a crystal, a resonator can also be con-

nected between OSC1 and OSC2 to get a fre-

quency reference, but two external capacitors

in OSC1 and OSC2 are required. If the internal

RC oscillator is used, the OSC1 and OSC2 can

be selected as general I/O lines or an 32768Hz

crystal oscillator (RTC OSC). Also, the frequen-

cies of the internal RC oscillator can be

3.2MHz, 1.6MHz, 800kHz and 400kHz (de-

pended by options).

The WDT oscillator is a free running on-chip RC

oscillator, and no external components are re-

quired. Even if the system enters the power down

mode, the system clock is stopped, but the WDT

oscillator still works with a period of approxi-

mately 72ms. The WDT oscillator can be disabled

by ROM code option to conserve power.

Watchdog Timer - WDT

The clock source of WDT is implemented by a

dedicated RC oscillator (WDT oscillator), RTC

clock or instruction clock (system clock divided

by 4), decided by ROM code option. This timer is

designed to prevent a software malfunction or

sequence from jumping to an unknown location

with unpredictable results. The Watchdog

Timer can be disabled by a ROM code option. If

the Watchdog Timer is disabled, all the execu-

tions related to the WDT result in no operation.

The RTC clock is enabled only in the internal

RC+RTC mode.

Once the internal WDT oscillator (RC oscillator

with a period of 72ms/5V normally) is selected, it

is first divided by 256 (8-stage) to get the nomi-

nal time-out period of approximately

18.4ms/5V. This time-out period may vary with

temperatures, VDD and process variations. By

invoking the WDT prescaler, longer time-out

periods can be realized. Writing data to WS2,

WS1, WS0 (bit 2,1,0 of the WDTS) can give differ-

ent time-out periods. If WS2, WS1, and WS0 are

all equal to 1, the division ratio is up to 1:128, and

the maximum time-out period is 2.4s/5V seconds.

If the WDT oscillator is disabled, the WDT clock

may still come from the instruction clock and op-

erate in the same manner except that in the

HALT state the WDT may stop counting and lose

its protecting purpose. In this situation the logic

can only be restarted by external logic. The high

nibble and bit 3 of the WDTS are reserved for

user's defined flags, which can be used to indicate

some specified status.

If the device operates in a noisy environment, us-

ing the on-chip RC oscillator (WDT OSC) or

32kHz crystal oscillator (RTC OSC) is strongly

recommended, since the HALT will stop the sys-

tem clock.

S yst e m C l o ck/ 4

8- bi t C ou nt er

W D T P r e sca l e r

7- bi t C o u n t e r

8- t o - 1 M U X

W D T T i m e - out

WS 0 ~ WS 2

RO M

C ode

Op t i o n

Se l e c t

WD T

OS C

RT C O S C

Watchdog Timer

HT48R10A Datasheet(PDF) 12 Page - Holtek Semiconductor Inc

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