DS1852

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A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is a stable LOW during the HIGH period of the acknowledge-related clock pulse.

Of course, setup and hold times must be taken into account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is

the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge

bit after each received byte.

2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the

command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a

number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit

after all received bytes other than the last byte. At the end of the last received byte, a ‘not

acknowledge’ can be returned.

The master device generates all serial clock pulses and the START and STOP conditions. A transfer is

ended with a STOP condition or with a repeated START condition. Since a repeated START condition

is also the beginning of the next serial transfer, the bus will not be released.

The DS1852 may operate in the following two modes:

1) Slave receiver mode: Serial data and clock are received through SDA and SCL, respectively. After

each byte is received, an acknowledge bit is transmitted. START and STOP conditions are

recognized as the beginning and end of a serial transfer. Address recognition is performed by

hardware after reception of the slave (device) address and direction bit.

2) Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.

However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial

data is transmitted on SDA by the DS1852 while the serial clock is input on SCL. START and STOP

conditions are recognized as the beginning and end of a serial transfer.

Slave Address: Command/control byte is the first byte received following the START condition from

the master device. The command/control byte consists of a 4-bit control code. For the DS1852, this is set

as 1010 000 (when ASEL is ‘0’) binary for R/W operations. The last bit of the command/control byte

(R/W) defines the operation to be performed. When set to a 1 a read operation is selected, and when set

to a 0 a write operation is selected.

Following the START condition, the DS1852 monitors the SDA bus checking the device type identifier

being transmitted. Upon receiving the chip address control code, and the R/W bit, the slave device

outputs an acknowledge signal on the SDA line.