AS4C64M16D3A datasheet(9/86 Pages) ALSC

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Functional Description

The DDR3 SDRAM is a high-speed dynamic random access memory internally configured as an eight-bank

DRAM. The DDR3 SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n Prefetch

architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A

single read or write operation for the DDR3 SDRAM consists of a single 8n-bit wide, four clock data transfer at the

internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.

Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and continue for a

burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration

of an Active command, which is then followed by a Read or Write command. The address bits registered coincident

with the Active command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A12

select the row). The address bit registered coincident with the Read or Write command are used to select the

starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10),

and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register.

Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined manner. The

following sections provide detailed information covering device reset and initialization, register definition, command

descriptions and device operation.

Figure 4. Reset and Initialization Sequence at Power-on Ramping

CK#

VDDQ

RESET#

tCKSRX

T=200µs

T=500µs

tDLLK

tXPR

tMRD

tMOD

tZQinit

MRS

Note 1

MRS

ZQCL

Note 1

VALID

MR3

MR2

MR1

MR0

VALID

VDD

COMMAND

CKE

ODT

RTT

Tmin=10ns

tIS

Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW

Don't Care

TIME BREAK

NOTE 1. From time point "Td" until "Tk " NOP or DES commands must be applied between MRS and ZQCL commands.

AS4C64M16D3A-12BIN

AS4C64M16D3A-12BCN

Confidential

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Rev.1.0 Aug.2016

AS4C64M16D3A Datasheet(PDF) 9 Page - Alliance Semiconductor Corporation

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