Online digital trimming procedure

SEA01

10/24

DocID024452 Rev 1

condition. START and STOP conditions are always generated by the master. The bus is

considered to be busy after the START condition. The bus is considered to be free again a

certain time after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In

this respect, the START (S) and repeated START (Sr) conditions are functionally identical

–

every byte put on the serial data line is 8 bits long

–

each byte is followed by an acknowledge bit

–

data is transferred with the most significant bit (MSB) first

–

data transfer with acknowledge is obligatory

The acknowledge-related clock pulse is generated by the master. The transmitter releases

the serial data line (HIGH) during the acknowledge clock pulse. The receiver pulls down the

serial data line during the acknowledge clock pulse so that it remains stable LOW during the

HIGH period of this clock pulse. Of course, setup and hold time must also be taken into

account.

When SEA01 is addressed, it generates an acknowledge after each byte has been

received. When SEA01 doesn't acknowledge its address, the data line is left HIGH by the

device. The master can then generate either a STOP condition to abort the transfer, or a

repeated START condition to start a new transfer.

If a SEA01-receiver does acknowledge its address but, sometime later in the transfer

cannot receive any more data bytes, the master must again abort the transfer. This is

indicated by SEA01 generating the not-acknowledge on the first byte to follow. SEA01

leaves the data line HIGH and the master generates a STOP or a repeated START

condition. If a master-receiver is involved in a transfer, it must signal the end of data to the

slave- transmitter by not generating an acknowledge on the last byte that was clocked out of

the slave. The slave-transmitter must release the data line to allow the master to generate a

STOP or repeated START condition.

Data transfers have the following format: after the START condition (S), a slave address is

sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W)

- a 'zero' indicates a transmission (WRITE), a 'one' indicates a request for data (READ). A

data transfer is always terminated by a STOP condition (P) generated by the master.

However, if a master still wishes to communicate on the bus, it can generate a repeated

START condition (Sr) and address the slave without first generating a STOP condition.

3.2

Device address

direction (R/W).

This address corresponds to <52> Hex.

MSB

LSB

A1

A2

A3

A4

A5

A6

A7

R/W

10

1

0

0

1

0

1/0